Patents by Inventor Vojislav Vukovie

Vojislav Vukovie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuits for implementing parity computation in a parallel architecture LDPC decoder
    Patent number: 8347167
    Abstract: A parity unit circuit for use in a parallel, pipelined, low density parity check (LDPC) decoder that implements an iterative, min-sum, message passing LDPC algorithm. The parity unit provides a memory logic block for storing information relating to a current and next iteration of the LDPC computations and includes a “compute 1” logic block for computing a parity message (with sign) for application to related bit nodes and a “compute2” logic block for updating the data stored in the memory logic block for a next iteration of the LDPC decoder.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: January 1, 2013
    Assignee: LSI Corporation
    Inventors: Alexander Andreev, Vojislav Vukovie, Igor Vikhliantsev
  • CIRCUITS FOR IMPLEMENTING PARITY COMPUTATION IN A PARALLEL ARCHITECTURE LDPC DECODER
    Publication number: 20100162071
    Abstract: A parity unit circuit for use in a parallel, pipelined, low density parity check (LDPC) decoder that implements an iterative, min-sum, message passing LDPC algorithm. The parity unit provides a memory logic block for storing information relating to a current and next iteration of the LDPC computations and includes a “compute 1” logic block for computing a parity message (with sign) for application to related bit nodes and a “compute2” logic block for updating the data stored in the memory logic block for a next iteration of the LDPC decoder.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 24, 2010
    Inventors: Alexander Andreev, Vojislav Vukovie, Igor Vikhliantsev