Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: A stackable tier structure comprising one or more integrated circuit die and one or more feedthrough structures is disclosed. The I/O pads of the integrated circuit die are electrically rerouted using conductive traces from the first side of the tier structure to a feedthrough structure comprising one ore more conductive structures. The conductive structures electrically route the integrated die pads to predetermined locations on the second side of the tier structure. The predetermined locations, such as exposed conductive pads or conductive posts, in turn, may be interconnected to a second tier structure or other circuitry to permit the fabrication of a three-dimensional microelectronic module comprising one or more stacked tiers.

Abstract: The present invention generally relates to integrating electronic components into an electro-active frame for driving electro-active focusing lenses. This is accomplished in a cosmetically pleasing manner that allows a platform of frame systems to be built from a single electronic module. Specifically, the present invention discloses controlling an electro-active lens in a deliberate, hands free manner that gives the user control of the electro-active lens.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A stackable tier structure comprising one or more integrated circuit die and one or more feedthrough structures is disclosed. The 1/0 pads of the integrated circuit die are electrically rerouted using conductive traces from the first side of the tier structure to a feedthrough structure comprising one ore more conductive structures. The conductive structures electrically route the integrated die pads to predetermined locations on the second side of the tier structure. The predetermined locations, such as exposed conductive pads or conductive posts, in turn, may be interconnected to a second tier structure or other circuitry to permit the fabrication of a three-dimensional microelectronic module comprising one or more stacked tiers.

Abstract: A stackable tier structure comprising one or more integrated circuit die and one or more feedthrough structures is disclosed. The I/O pads of the integrated circuit die are electrically rerouted using conductive traces from the first side of the tier structure to a feedthrough structure comprising one ore more conductive structures. The conductive structures electrically route the integrated die pads to predetermined locations on the second side of the tier structure. The predetermined locations, such as exposed conductive pads or conductive posts, in turn, may be interconnected to a second tier structure or other circuitry to permit the fabrication of a three-dimensional microelectronic module comprising one or more stacked tiers.

Abstract: An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration having multiple layers. A connection layer is provided for connecting the module to an external system. A configurable logic device is provided for routing connections between the integrated circuit and the connection layer. Specifically, the configurable logic device is programmable to create logical circuits connecting at least one of the input/output connectors of the integrated circuit to at least one of the input/output connectors of the connection layer. Configuration information for programming the reconfigurable logic device is stored in a memory within the module.

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A sensor system (30) has a sensor module (10) and a receiver module (45). The sensor module (10) functions as a wireless data collection device and has a flexible thin sheet of silicon (60, 65, 70) comprising circuitry (71, 72, 73), a flexible power source (105), and a flexible support substrate (55). The silicon, power source, and flexible support substrate are integrated as layers of the sensor module (10). The layers are placed together in the form of an adhesive bandage (10). A plurality of electrodes (80) are connected to the sensor module (10) and protrude from the flexible substrate (55) for contacting the skin of a subject body (20). The receiver module (45) includes one of an RF receiver with a wireless port for continuously receiving data (40), or a physical I/O port (87) to which the sensor module (10) can be physically connected for downloading stored data from the sensor module (10).

Abstract: A high-frequency, low-temperature regenerator (12). The regenerator (12) includes a substrate (50) having rare earth material (52) disposed thereon. In a specific embodiment, the substrate (50) has channels or pores (54) therethrough or therein to facilitate gas flow through the regenerator (12). The substrate (50) is constructed from a material, such as polyimide, polyester, or stainless steel, which is sufficient to define the geometry of the regenerator (12). The rare earth material (52) is selected and deposited on the substrate (50) in a layer (52) having thermal penetration depth that is greater than the thickness of the layer (52). The thermal penetration depth is sufficiently high to enable all of the rare earth material (52) to contribute to thermal regeneration at an operating frequency of 30 Hz. In the illustrative embodiment, the thickness of the substrate (50) is less than or equal to approximately 0.001 inches. The layer of rare earth material (52) is approximately 0.0002 inches thick.