Patents by Inventor Volker Berghof

Volker Berghof has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect structures and methods
    Patent number: 8097955
    Abstract: Interconnect structures and methods are disclosed. In one embodiment, an interconnect structure includes a via extendable through a workpiece from a first side of the workpiece to a second side of the workpiece. The via is partially filled with a conductive material and has sidewalls. The interconnect structure includes a contact coupled to the conductive material in the via proximate the first side of the workpiece. The conductive material in the via comprises a recessed region comprising a landing zone proximate the second side of the workpiece.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: January 17, 2012
    Assignee: Qimonda AG
    Inventors: Bernd Zimmermann, Volker Berghof, Stefan Ruckmich, Thorsten Schedel
  • Interconnect Structures and Methods
    Publication number: 20100090317
    Abstract: Interconnect structures and methods are disclosed. In one embodiment, an interconnect structure includes a via extendable through a workpiece from a first side of the workpiece to a second side of the workpiece. The via is partially filled with a conductive material and has sidewalls. The interconnect structure includes a contact coupled to the conductive material in the via proximate the first side of the workpiece. The conductive material in the via comprises a recessed region comprising a landing zone proximate the second side of the workpiece.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 15, 2010
    Inventors: Bernd Zimmermann, Volker Berghof, Stefan Ruckmich, Thorsten Schedel
  • Method for Enhancing the Adhesion of a Passivation Layer on a Semiconductor Device
    Publication number: 20090166848
    Abstract: In a method for making a semiconductor component, an integrated circuit is provided with a chip pad on an active side. A conductive track is connected to the chip pad and a passivation layer covers the conductive track. Forming the conductive track includes structuring an uneven sidewall for form closure with the passivation layer.
    Type: Application
    Filed: December 29, 2007
    Publication date: July 2, 2009
    Inventors: Volker Berghof, Thorsten Schedel