Patents by Inventor Volker Graf

Volker Graf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5938295
    Abstract: An electronic control unit adjusts the pressure in the brake cylinders of at least one axle during the braking process on the basis of measured static and dynamic loads at the other axle.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: August 17, 1999
    Assignee: Robert Bosch GmbH
    Inventors: Werner Stumpe, Andreas Schlichenmaier, Heinz Kaechele, Volker Graf, Bernhard Schwendemann, Juergen Wrede
  • Patent number: 5439876
    Abstract: A method for making layered structures of artificial high T.sub.c superconductor compounds by which on top of a seed crystal having a lattice structure matching the lattice structure of the superconductor compound to be made, oxide layers of all constituent components are epitaxially grown in a predetermined sequence so as to create a sandwich structure not found in natural crystals. The epitaxial deposition of the constituent components is performed in a reaction chamber having evaporation facilities, inlets for metal-organic gases, and inlets for background gases including oxygen.
    Type: Grant
    Filed: August 16, 1993
    Date of Patent: August 8, 1995
    Assignee: International Business Machines Corporation
    Inventors: Volker Graf, Carl A. Mueller
  • Patent number: 5037776
    Abstract: A method, and devices produced therewith, for the epitaxial growth of sub-micron semiconductor structures with at least one crystal plane-dependently grown, buried active layer (24) consisting of a III-V compound. The active layer (24) and adjacent embedding layers (23, 25) form a heterostructure produced in a one-step growth process not requiring removal of the sample from the growth chamber in between layer depositions. The layers of the structure are grown on a semiconductor substrate (21) having a structured surface exposing regions of different crystal orientation providing growth and no-growth-planes for the selective growth process. The method allows the production of multiple, closely spaced active layers and of layers consisting of adjoining sections having different physical properties.
    Type: Grant
    Filed: September 14, 1989
    Date of Patent: August 6, 1991
    Assignee: International Business Machines Corporation
    Inventors: Yvan Galeuchet, Volker Graf, Wilhelm Heuberger, Peter Roentgen
  • Patent number: 4732871
    Abstract: Process for producing temperature-stable undercut profiles for use in semiconductor fabrication. The process is based on the phenomenon of high etch-rate selectivity between RF- and LF- PECVD-grown silicon nitride films (12G and 13G, respectively) that are deposited on top of each other. By choosing proper film and process parameters, these PECVD nitride structures can be made stress-free: the tensile stress of the RF film (12G) compensates the compressive stress of the LF film (13G).Also disclosed is an application of a T-shaped structure (15), produced with the new process, in a method for fabricating fully self-aligned "dummy" gate sub-micron MESFETs.
    Type: Grant
    Filed: March 30, 1987
    Date of Patent: March 22, 1988
    Assignee: International Business Machines Corporation
    Inventors: Peter L. Buchmann, Volker Graf, Peter D. Hoh, Theodor O. Mohr, Peter Vettiger
  • Patent number: 4728621
    Abstract: A process for the fabrication of "low temperature"-gate MESFET structures, i.e., gate metal deposition takes place after annealing of an n.sup.+ -implant that form source- and drain- contact regions. The process permits self-alignment of all three important MESFET parts, namely, the implanted contact regions, and both, the ohmic, as well as the gate, contact metallizations. In the process, a multi-layer "inverted-T" structure is used as a mask for the n.sup.+ -implant and for the ohmic and gate metallizations. The upper part of the "inverted-T" is a so-called dummy gate which is replaced by the Schottky gate after ohmic contact metal deposition. The source-gate and drain-gate separations are determined by the shoulders of the lower layer of the "inverted-T", the shoulders being obtained using sidewall techniques.
    Type: Grant
    Filed: November 24, 1986
    Date of Patent: March 1, 1988
    Assignee: International Business Machines Corporation
    Inventors: Volker Graf, Albertus Oosenbrug
  • Patent number: 4647954
    Abstract: The transistor comprises two electrodes, source (12) and drain (13), with a semiconductor tunnel channel (11) arranged therebetween. A gate (14) for applying control signals is coupled to the channel. The semiconductor, at low temperatures, behaves like an insulator with a low barrier (some meV) through which charge carriers can tunnel under the influence of an applied drain voltage. The tunnel current can be controlled by a gate voltage V.sub.G which modifies the barrier height between source and drain thereby changing the tunnel probability.
    Type: Grant
    Filed: September 27, 1984
    Date of Patent: March 3, 1987
    Assignee: International Business Machines Corporation
    Inventors: Volker Graf, Pierre L. Gueret, Carl A. Mueller