Abstract: A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprised providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.

Abstract: A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprises providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.

Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Abstract: The present invention comprises a programmable interconnect cell switching circuit structure having a control gate potential node, a first floating gate flash transistor with a drain, a source, a floating gate and a control gate connected to the control gate potential node and a second floating gate flash memory transistor having a drain connected to a first programming node, a drain connected to a second programming node, a floating gate connected to the floating gate of the first floating gate flash transistor and a control gate connected to the control gate potential node, whereby either the source or the drain of the first floating gate flash transistor need to be connected outside the cell to ground during the program operation.

Abstract: The present invention provides for a method of testing an FPGA using NVM memory cells for programmable interconnects. The NVM memory cells are arranged as a memory array of rows and columns. User-configurable logic elements and interconnections, which are programmed by the stored states of the memory cells, are organized into identical and/or differing tiles. The tiles organized into an array of rows and columns superimposed upon the memory array. The testing method includes: selecting test circuit configurations by which identical tiles are identically programmed as much as possible; and simultaneously programming and simultaneously erasing pluralities of the memory rows corresponding to the tiles into the test circuit configurations. Additionally, the test circuit configurations programmed into the FPGA are tested at a lower supply voltage than that of normal operation.

Abstract: The present invention provides for a method of testing an FPGA using NVM memory cells for programmable interconnects. The NVM memory cells are arranged as a memory array of rows and columns. User-configurable logic elements and interconnections, which are programmed by the stored states of the memory cells, are organized into identical and/or differing tiles. The tiles are organized into an array of rows and columns superimposed upon the memory array. The testing method includes: selecting test circuit configurations by which identical tiles are identically programmed as much as possible; and simultaneously programming and simultaneously erasing pluralities of the memory rows corresponding to the tiles into the test circuit configurations. Additionally, the test circuit configurations programmed into the FPGA are tested at a lower supply voltage than that of normal operation.

Abstract: Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor. The source/drains of the sense field effect transistor are formed from buried doped layers (e.g. N+ in a P-doped substrate) which are formed prior to formation of the polysilicon floating gate and control gate. Lateral diffusion of dopant from the buried source/drains into the channel beneath the floating gate facilitates electron tunneling during erase and program operations, and the graded junctions of the buried source/drains lower band-to-band tunneling leakage.

Abstract: In an FPGA, nonvolatile reprogrammable interconnect cells which have a switch transistor and at least one second transistor for programming and sensing, or a second transistor for sensing and a buried N+ region for programming the cell, use a high voltage on the common control gate for the cell erasing operation. The source/drains of the switch transistor are grounded. By placing an intermediate voltage on the source/drains of the second transistor, erase times can be reduced and test costs can be significantly lowered.

Abstract: Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.