Patents by Inventor Volker Mauer

Volker Mauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10136384
    Abstract: Integrated circuits with wireless communications circuitry are provided. The wireless communications circuitry may include an input FIFO, an output FIFO, a processing module interposed between the input and output FIFOs, and dynamic power control circuitry that controls the performance of the processing module. The input and output FIFOs may provide fill level information to the processing module. The dynamic power control circuitry may analyze the current fill level information received from the input and output FIFOs and may increase the operating frequency and/or boost the power supply voltage of the processing module in response to detecting that the input FIFO is filling up faster than the output FIFO or may decrease the operating frequency and/or reduce the power supply voltage of the processing module in response to detecting that the output FIFO is filling up faster than the input FIFO.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: November 20, 2018
    Assignee: Altera Corporation
    Inventor: Volker Mauer
  • Patent number: 10003341
    Abstract: An arithmetic processing block in which two inputs are provided for a multiplier, the block also including a pre-adder for combining the inputs to provide an additional option for a multiplier input.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: June 19, 2018
    Assignee: Altera Corporation
    Inventor: Volker Mauer
  • Patent number: 9966933
    Abstract: A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.
    Type: Grant
    Filed: May 21, 2016
    Date of Patent: May 8, 2018
    Assignee: ALTERA CORPORATION
    Inventors: Volker Mauer, Martin Langhammer
  • Patent number: 9748928
    Abstract: Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use, e.g., in multiple instances of the DSP block circuitry on the IC, for implementing finite-impulse-response (“FIR”) filters that are dynamically adjustable. Advantages of such DSP block circuitries may include an increase in performance and a reduction in logic and memory usage for multi-standard FIR filters.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: August 29, 2017
    Assignee: Altera Corporation
    Inventor: Volker Mauer
  • Patent number: 9660624
    Abstract: Circuitry that efficiently implements loop functions in an integrated circuit is provided. The circuitry combines a feed-forward circuit with a feedback loop that includes a unit delay element in a feedback path. The feedback path may couple the output of a processing element to the input of the processing element. The processing element may implement a function that satisfies commutative, associative, and distributive properties. Combining the feedback loop with the feed-forward circuit may allow for register retiming in the feedback loop and for register pipelining with optional register retiming in the feed-forward circuit. The circuitry may thus trade off an increase in throughput and clock frequency for additional resources.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 23, 2017
    Assignee: Altera Corporation
    Inventors: Nima Safari, Volker Mauer, Shahin Gheitanchi
  • Patent number: 9485129
    Abstract: Integrated circuits with wireless communications circuitry having peak cancelation circuitry operable to perform crest factor reduction is provided. The peak cancelation circuitry may receive at least first and second carrier waveforms and may include at least a first canceling pulse generator (CPG), a second CPG, a first peak detector for performing peak detection on the first waveform, a second peak detector for performing peak detection on the second waveform, a third peak detector for performing peak detection on a combined waveform of the first and second waveforms, and a pulse allocator that receives clipping information from the three peak detectors and that controls the amount of peak cancelation that is being performed by the two CPGs. The allocator may determine whether the combined waveform contains any peaks. In response to determining that the combined waveform does not contain any peaks, the CPGs may be configured in bypass mode.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: November 1, 2016
    Assignee: Altera Corporation
    Inventors: Benjamin Thomas Cope, Volker Mauer, Shahin Gheitanchi, Nima Safari
  • Patent number: 9438203
    Abstract: Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use, e.g., in multiple instances of the DSP block circuitry on the IC, for implementing finite-impulse-response (“FIR”) filters that are dynamically adjustable. Advantages of such DSP block circuitries may include an increase in performance and a reduction in logic and memory usage for multi-standard FIR filters.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: September 6, 2016
    Assignee: Altera Corporation
    Inventor: Volker Mauer
  • Patent number: 9379687
    Abstract: A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: June 28, 2016
    Assignee: ALTERA CORPORATION
    Inventors: Volker Mauer, Martin Langhammer
  • Patent number: 9337782
    Abstract: Integrated circuits are provided with wireless communications circuitry having digital predistortion (DPD) circuitry, peak canceling circuitry, a power amplifier, and signal conditioning circuitry for controlling the DPD and peak canceling circuitry. The peak canceling circuitry may receive transmit signals and may clip peaks in the transmit signals that exceed a magnitude threshold value. The DPD circuitry may compensate for non-linear characteristics of the power amplifier by outputting a predistorted version of the clipped transmit signals. The power amplifier may receive the predistorted signals and may perform amplification to generate amplified signals. The signal conditioning circuitry may identify power transfer characteristics of the power amplifier and DPD circuitry using the predistorted signals and the amplified signals.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 10, 2016
    Assignee: Altera Corporation
    Inventors: Volker Mauer, Nima Safari, Shahin Gheitanchi, Richard Maiden
  • Patent number: 9036734
    Abstract: Integrated circuits with wireless communications circuitry having digital predistortion (DPD) circuitry are provided. The digital predistortion circuitry may include a forward path filter, a time domain alignment (TDA) circuit, a frequency domain alignment (FDA) circuit, and an adaption circuit. The TDA circuit may receive power amplifier input signals and power amplifier output signals and may include a cross correlator, a peak detector, and a delay circuit for performing coarse time domain alignment (i.e., to align the power amplifier input and output signals). The FDA circuit may include a fast Fourier transform circuit, a matrix multiplier, and a matrix inverter for performing frequency domain alignment. The adaption circuit may analyze the aligned signals output from the FDA circuit to produce impulse response coefficients that are then used to control the forward path filter. The forward path filter may serve to predistort transmit signals prior to radio-frequency amplification.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: May 19, 2015
    Assignee: Altera Corporation
    Inventors: Volker Mauer, Shahin Gheitanchi, Benjamin Thomas Cop
  • Patent number: 8959136
    Abstract: Efficient matrix operations circuitry is based on combining a matrix decomposition and a forward substitution operations to share the same processing overhead. A dual multiplier circuit selectively applies complex multiplication operations to a first and second input vectors for computing a conjugate dot product vector or a non-conjugate dot product vector. The conjugate dot product vector corresponds to the matrix decomposition operation for triangulating an input matrix to generate an element of a triangulated matrix. The non-conjugate dot product vector corresponds to a forward substitution operation for determining an element of a forward substitution vector from the triangulated matrix.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: February 17, 2015
    Assignee: Altera Corporation
    Inventors: Colman C. Cheung, Steven Perry, Volker Mauer, Mark Jervis
  • Patent number: 8914716
    Abstract: A state metric calculator for calculating state metrics of stages in a trellis of a sequence estimation technique is described. The calculator has a processing path containing operations needed for calculating a state metric of a trellis stage from state metrics of an earlier trellis stage. One or more data stores are located in the processing path to divide the path into separate sections. The sections can then operate on the production of different state metrics to one another in, if desired, the same clock cycle.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: December 16, 2014
    Assignee: Altera Corporation
    Inventors: Volker Mauer, Zhengjun Pan
  • Patent number: 8812576
    Abstract: Circuitry for performing QR decomposition of an input matrix includes multiplication/addition circuitry for performing multiplication and addition/subtraction operations on a plurality of inputs, division/square-root circuitry for performing division and square-root operations on an output of the multiplication/addition circuitry, a first memory for storing the input matrix, a second memory for storing a selected vector of the input matrix, and a selector for inputting to the multiplication/addition circuitry any one or more of a vector of the input matrix, the selected vector, and an output of the division/square-root circuitry. On respective successive passes, a respective vector of the input matrix is read from a first memory into a second memory, and elements of a respective vector of an R matrix of the QR decomposition are computed and the respective vector of the input matrix in the first memory is replaced with the respective vector of the R matrix.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: August 19, 2014
    Assignee: Altera Corporation
    Inventor: Volker Mauer
  • Patent number: 8751551
    Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: June 10, 2014
    Assignee: Altera Corporation
    Inventors: Keone Streicher, Martin Langhammer, Yi-Wen Lin, Wai-Bor Leung, David Lewis, Volker Mauer, Henry Y. Lui, Suleyman Sirri Demirsoy, Hyun Yi
  • Publication number: 20140082035
    Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
    Type: Application
    Filed: November 21, 2013
    Publication date: March 20, 2014
    Applicant: Altera Corporation
    Inventors: Keone Streicher, Martin Langhammer, Yi-Wen Lin, Wai-Bor Leung, David Lewis, Volker Mauer, Henry Y. Lui, Suleyman Sirri Demirsoy, Hyun Yi
  • Patent number: 8620980
    Abstract: A specialized multiplier block in a programmable device incorporates multipliers and adders, and is configurable as one or more types of finite impulse response (FIR) filter including a Direct Form II FIR filter. The specialized multiplier block further includes input and output registers to allow chaining of Direct Form II FIR filters into longer Direct Form II FIR filters. An output accumulator also allows the specialized multiplier block to operate as a time-division multiplexed FIR filter, performing several filtering operations during each clock cycle of the programmable device.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: December 31, 2013
    Assignee: Altera Corporation
    Inventors: Volker Mauer, Martin Langhammer
  • Patent number: 8620977
    Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: December 31, 2013
    Assignee: Altera Corporation
    Inventors: Keone Streicher, Martin Langhammer, Yi-Wen Lin, Wai-Bor Leung, David Lewis, Volker Mauer, Henry Y. Lui, Suleyman Sirri Demirsoy, Hyun Yi
  • Publication number: 20130332497
    Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
    Type: Application
    Filed: August 7, 2013
    Publication date: December 12, 2013
    Applicant: Altera Corporation
    Inventors: Keone Streicher, Martin Langhammer, Yi-Wen Lin, Wai-Bor Leung, David Lewis, Volker Mauer, Henry Y. Lui, Suleyman Sirri Demirsoy, Hyun Yi
  • Patent number: 8583715
    Abstract: A programmable integrated circuit device can be configured as a cascaded integrator-comb (CIC) filter. In order to take advantage of Hogenauer pruning to configure the CIC filter efficiently, a software tool for configuring the device can be provided in which the Fj terms for Hogenauer pruning have been calculated in advance for all possible user parameters supported by the tool. To configure a CIC filter, the user enters the parameters in the tool, which then looks up the Fj terms corresponding to those parameters and completes the calculation of the Bj terms for Hogenauer pruning. Because the calculation of the Fj terms is the most time-consuming step in calculating of the Bj terms, pre-calculation of the Fj terms, which can be done just once by the provider of the tool, allows end users to calculate the Bj terms in reasonable periods of time, making Hogenauer pruning available to end users.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: November 12, 2013
    Assignee: Altera Corporation
    Inventors: Zhengjun Pan, Volker Mauer
  • Patent number: 8578255
    Abstract: A sequence estimator is described. In one embodiment, the sequence estimator includes a plurality of maximum a posteriori probability (MAP) decoding engines each arranged to process a series of windows of a transmitted signal where state metrics produced for an end of one window by one decoding engine are re-used for the initialization of a state metric calculation process performed by another decoding engine on another window of the signal.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: November 5, 2013
    Assignee: Altera Corporation
    Inventors: Zhengjun Pan, Volker Mauer