Abstract: An apparatus for providing oscillator signals includes an oscillator circuit configured to generate a first oscillator signal with a first oscillator signal frequency for a frequency conversion of a first signal to be converted and to generate a second oscillator signal with a second oscillator signal frequency for a frequency conversion of a second signal to be converted. The oscillator circuit is configured to enable the generation of the first oscillator signal with the first oscillator signal frequency and the second oscillator signal with the second oscillator signal frequency based on at least two different possible oscillator circuit configurations. The control circuit is configured to select, based on the first oscillator signal frequency and the second oscillator signal frequency, one of the possible oscillator circuit configurations of the oscillator circuit for generating the first oscillator signal and the second oscillator signal.

Abstract: An apparatus for providing oscillator signals includes an oscillator circuit configured to generate a first oscillator signal with a first oscillator signal frequency for a frequency conversion of a first signal to be converted and to generate a second oscillator signal with a second oscillator signal frequency for a frequency conversion of a second signal to be converted. The oscillator circuit is configured to enable the generation of the first oscillator signal with the first oscillator signal frequency and the second oscillator signal with the second oscillator signal frequency based on at least two different possible oscillator circuit configurations. The control circuit is configured to select, based on the first oscillator signal frequency and the second oscillator signal frequency, one of the possible oscillator circuit configurations of the oscillator circuit for generating the first oscillator signal and the second oscillator signal.

Abstract: Some embodiments of the present disclosure relate to multiband receivers that include at least one divider unit having a divisor that is other-than-two. For example, in some embodiments the divisor is an odd integer (e.g., three). Such divisors allow oscillators for respective receiver subunits in a multi-band receiver to have frequencies that are sufficiently different from one another so as to limit cross-talk interference there between, even when the receiver subunits are concurrently receiving data on adjacent channels. To facilitate this other-than-two divisor, a phase error compensation block is often used to compensate for the effects of using the other-than-two divisor.

Abstract: Some embodiments of the present disclosure relate to multiband receivers that include at least one divider unit having a divisor that is other-than-two. For example, in some embodiments the divisor is an odd integer (e.g., three). Such divisors allow oscillators for respective receiver subunits in a multi-band receiver to have frequencies that are sufficiently different from one another so as to limit cross-talk interference there between, even when the receiver subunits are concurrently receiving data on adjacent channels. To facilitate this other-than-two divisor, a phase error compensation block is often used to compensate for the effects of using the other-than-two divisor.

Abstract: A device may include an oscillator circuit, a control circuit, a frequency detector circuit, and a processor circuit. The oscillator circuit may include a frequency control input to output an oscillator signal. The frequency of the oscillator signal depends on an input signal applied to the frequency control input. The control circuit is configured to apply a first input signal value, a second input signal value, and a third input signal value to the frequency control input. The frequency detector circuit is configured to detect the first frequency value of the oscillator signal when the first input signal value is applied to the frequency control input, a second frequency value of the oscillator signal when the second input signal value is applied to the frequency control input, and a third frequency value of the oscillator signal when the third input signal value is applied to the frequency control input.

Abstract: A device comprises an oscillator circuit, a control circuit, a frequency detector circuit, and a processor circuit. The oscillator circuit comprises a frequency control input and is configured to output an oscillator signal. The frequency of the oscillator signal depends on an input signal applied to the frequency control input. The control circuit is configured to apply a first input signal value, a second input signal value, and a third input signal value to the frequency control input. The frequency detector circuit is configured to detect the first frequency value of the oscillator signal when the first input signal value is applied to the frequency control input, a second frequency value of the oscillator signal when the second input signal value is applied to the frequency control input, and a third frequency value of the oscillator signal when the third input signal value is applied to the frequency control input.

Abstract: A phase/frequency detector has a modulo counter for outputting a counter word with a predetermined word length depending on an oscillator signal. In addition, a modulo integrator for outputting an integrator word with the predetermined word length as a function of integration of a channel word is provided. The phase/frequency detector also has a difference element for outputting a phase error word with the predetermined word length as a function of a difference between the counter word and the integrator word.

Abstract: A digitally controlled oscillator device includes a programming input, a selection input and an oscillator core with a first capacitive element which is frequency determining and programmable. The first capacitive element is coupled to the programming input that receives a first data word by which an oscillating frequency of the oscillator device is programmed with a predetermined frequency step size. The oscillator device further includes a selection unit for selecting a mode which is coupled to the selection input that receives a mode selection signal. The mode is selectable from a plurality of modes depending on the mode selection signal and each mode from the plurality of modes is characterized by a predetermined frequency step size. The digitally controlled oscillator device also includes a deattenuation amplifier.

Abstract: A sigma-delta modulator is supplied with a data word and includes a first and at least one further modulation stage, each having at least two adders. The adders in the first modulation stage process a low-significance component and a delayed more significant component of the data word and provide a result word and a carry at their respective outputs. The adders in the at least one further modulation stage process a low-significance component and a more significant component of the result word and provide a further result word and a carry at their respective outputs. The low-significance component and the more significant component of the result word are provided to the further modulation stages with an unvarying delay. A bit stream is derived from a carry from final instances of the at least two adders in the first modulation stage and in the further modulation stage respectively.

Abstract: A phase/frequency detector has a modulo counter for outputting a counter word with a predetermined word length depending on an oscillator signal. In addition, a modulo integrator for outputting an integrator word with the predetermined word length as a function of integration of a channel word is provided. The phase/frequency detector also has a difference element for outputting a phase error word with the predetermined word length as a function of a difference between the counter word and the integrator word.

Abstract: A data latch contains a supply connection, a reference ground potential connection and a data input. The input side of an inverter is connected to the data input, and it is coupled via a first switching device to the supply connection, and via a second switching device to the reference ground potential connection. Furthermore, a first multivibrator circuit having transistors of a first conductance type is provided, and is coupled to the supply connection. A second multivibrator circuit having transistors of a second conductance type is coupled to the reference ground potential connection. The transistors in the first and second multivibrator circuits in the data latch are connected to one another on the output side at a first node and at a second node, with the first node being connected to one output of the inverter, and the second node forming an output tap.

Abstract: A sigma-delta modulator is supplied with a data word and includes a first and at least one further modulation stage, each having at least two adders. The adders in the first modulation stage process a low-significance component and a delayed more significant component of the data word and provide a result word and a carry at their respective outputs. The adders in the at least one further modulation stage process a low-significance component and a more significant component of the result word and provide a further result word and a carry at their respective outputs. The low-significance component and the more significant component of the result word are provided to the further modulation stages with an unvarying delay. A bit stream is derived from a carry from final instances of the at least two adders in the first modulation stage and in the further modulation stage respectively.

Abstract: A digitally controlled oscillator device includes a programming input, a selection input and an oscillator core with a first capacitive element which is frequency determining and programmable. The first capacitive element is coupled to the programming input that receives a first data word by which an oscillating frequency of the oscillator device is programmed with a predetermined frequency step size. The oscillator device further includes a selection unit for selecting a mode which is coupled to the selection input that receives a mode selection signal. The mode is selectable from a plurality of modes depending on the mode selection signal and each mode from the plurality of modes is characterized by a predetermined frequency step size. The digitally controlled oscillator device also includes a deattenuation amplifier.

Abstract: A data latch contains a supply connection, a reference ground potential connection and a data input. The input side of an inverter is connected to the data input, and it is coupled via a first switching device to the supply connection, and via a second switching device to the reference ground potential connection. Furthermore, a first multivibrator circuit having transistors of a first conductance type is provided, and is coupled to the supply connection. A second multivibrator circuit having transistors of a second conductance type is coupled to the reference ground potential connection. The transistors in the first and second multivibrator circuits in the data latch are connected to one another on the output side at a first node and at a second node, with the first node being connected to one output of the inverter, and the second node forming an output tap.