Abstract: The invention relates to a control means for controlling burst accesses to a synchronous dynamic semiconductor memory device comprising at least two memory banks. In order to avoid relatively large time losses due to preparation cycles (precharge and activate), the invention provides an address converter unit (12) for converting a logical access address into physical access addresses by splitting the burst access into at least two partial burst accesses, wherein a first physical access address addresses a first memory area of a first memory bank for a first partial burst access and wherein a second physical access address addresses a second memory area of a second memory bank for a second partial burst access.

Abstract: The invention relates to a control means for controlling burst accesses to a synchronous dynamic semiconductor memory device comprising at least two memory banks. In order to avoid relatively large time losses due to preparation cycles (precharge and activate), the invention provides an address converter unit (12) for converting a logical access address into physical access addresses by splitting the burst access into at least two partial burst accesses, wherein a first physical access address addresses a first memory area of a first memory bank for a first partial burst access and wherein a second physical access address addresses a second memory area of a second memory bank for a second partial burst access.