Abstract: In order to test digital modules with functional elements, these are divided into test units (3) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (3), and the test responses resulting from this are evaluated at the outputs of the test unit (3). The effect is then encountered that changes at each of the inputs of a test unit (3) do not all affect a particular output of this test unit (3). For every output of the test unit (3), it is possible to define a cone (5) whose apex is formed by the particular output of the test unit (3) and whose base comprises the inputs of the test unit (3) where, and only where, changes affect the particular output. According to the invention, the test pattern to be applied to the inputs of the test unit (3) is constructed of sub-patterns, whose length is in particular ? the number of inputs of the test unit (3) that are contained in the base of a cone (5).

Abstract: An integrated memory and method for testing an integrated memory is provided herein. In order to test an integrated memory having a main data memory with a plurality of data memory units, a data memory unit is addressed and input test data for testing the addressed data memory unit are applied to the main data memory. The output test data are read out from the main data memory and compared with expected desired output test data in a self-test unit. Deviations detected during the comparison are buffer-stored in a redundancy analysis memory. These information items buffer-stored in the redundancy analysis memory are read out and transferred to a computing unit. In the computing unit, the defect positions in the output test data are identified, and a repair strategy is determined by means of redundant rows and/or redundant columns and/or redundant words provided. The redundant words required for the repair strategy are written to the redundancy analysis memory and activated.

Abstract: A circuit for test pattern generation compression of circuits with a built-in self-test function has a test data coupling circuit having a test data input for receiving a test data input signal from a circuit cell connected upstream, which signal can be stored in a test data buffer store, a data input for applying a data input signal, which can be stored in a buffer store, a test data output for outputting the buffer-stored test data signal, and a data output for outputting the buffer-stored data signal to a data signal path via a data signal output of the circuit cell, the two buffer stores of the test data coupling circuit having a common feedback signal path, via which the received test data input signal can be coupled into the data signal path depending on a first control signal applied to the test data coupling circuit.

Abstract: The invention relates to an integrated bus signal hold cell that is coupled with a bus line via a common input/output, and that has at least two inverters for holding the last state of the bus line. The outputs of the inverters are coupled with each other's inputs, respectively. The input of the first inverter is coupled with the input/output. The output of the second inverter is coupled with the input/output. An additional input is provided via which the bus signal hold cell can be charged with a defined test signal. The invention also relates to an integrated bus system and a method for driving a bus signal hold cell and a bus system.

Abstract: A data memory including a main data memory having a plurality of data memory units, a redundancy data memory that includes a plurality of redundancy data memory units for the replacement of defective data memory units of the main data memory, and a redundancy control logic for controlling the access to the redundancy data memory, the main data memory and the redundancy data memory being connected to a data bus in parallel with one another via data lines, and the main data memory and the redundancy control logic being connected, in parallel with one another, via address lines, to an address bus for the addressing of data memory units in the data memory.

Abstract: A semiconductor memory device includes a plurality of integrated circuit modules each having a plurality of module elements and at least one adjustable module element. At least one fuse box is electrically connected to the plurality of integrated circuit modules. The fuse box has a plurality of programmable fuse elements, that, when programmed, adjust the adjustable module element.

Abstract: The circuit cell for test methods having a built-in self-test function for modular circuits. The cell has a memory unit for storing data, a combinatorial logic circuit for data processing, and a memory control unit for controlling the memory unit. The memory control unit can be configured such that it sets the memory unit as a test pattern generator in a transmission mode and sets it as a test pattern compression device in a reception mode. The memory control unit produces a synchronizing signal for synchronizing the memory unit on the basis of communication signals which are interchanged by the memory control unit and memory control units in further circuit cells. With these methods, a transmission circuit cell is synchronized locally, so that a global clock signal is not required.

Abstract: The testable read-only memory for data memory redundant logic has read-only memory units for storage of determined fault addresses of faulty data memory units. The serviceability of each read-only memory unit can be checked by application of input test data and by comparison of read output test data with expected nominal output test data.