Abstract: A processor unit for a data-processing-aided electronic control system in a motor vehicle, in which the processor unit operates in real-time and contains within its functional structure a scalable computing unit and a vehicle interface unit, as well as (preferably) a communication coprocessor as separate structural components.

Abstract: A processor unit for a data-processing-aided electronic control system in a motor vehicle, in which the processor unit operates in real-time and contains within its functional structure a scalable computing unit and a vehicle interface unit, as well as (preferably) a communication coprocessor as separate structural components.

Abstract: For read-only storages and in particular for PLA applications, improved coupling elements together with an associated personalization scheme permit the storing of at least two memory (or logic) connection patterns selectable independently of each other. Quick electrical switching between at least two functional modes in the same storage array, is also provided. One device field effect transistor (FET) cells with specific gate configurations depending on the respective personalization state are used as coupling elements. For instance, in a two-fold personalization permanent storage, the coupling elements consist of FETs with two gate sections provided one beside the other. For a connection to be established in only one of the two possible functions at the respective crosspoint, one of the gate sections is connected to the control line provided for the functional selection. The remaining gate section is connected to the associated input line.

Abstract: Error detection and correction apparatus for a programmable logic array (PLA) having AND and OR logic combinations merged therein is disclosed. The output lines from the AND and OR logic elements are coupled in such a manner that their functions form complete groups containing, if possible, all minterms. Missing minterms are added, as necessary, by special output lines or logic elements provided for that purpose to complete a group. If a minterm occurs on two or more function lines, the corresponding minterm is entered as a correction term into an error detection logic means, one of which is associated with each group of logic output lines. The error detection logic means are also utilized to test whether one, and only one, of the output lines in a grouping of function lines has a binary 1 value.Error correction signals are generated by mixed group error detection means, the inputs of which are connected to a function line of another function group.