Abstract: An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.

Abstract: The present invention is a converter stage for converting a differential logic input signal and a corresponding common mode differential logic signal each having a first single-ended logic signal and a complementary second single-ended logic signal into a single-ended logic output signal. The converter stage comprises a first and a second differential stage each having a first and a second MOS transistor and a first and second current source for the differential stages. According to the invention the current sources are controlled by the voltage level which is centered between the mid-potentials of the common mode level differential logic signal and the mid-potential of the differential logic input signal.

Abstract: An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.

Abstract: The present invention is a converter stage for converting a differential logic input signal and a corresponding common mode differential logic signal each having a first single-ended logic signal and a complementary second single-ended logic signal into a single-ended logic output signal. The converter stage comprises a first and a second differential stage each having a first and a second MOS transistor and a first and second current source for the differential stages. According to the invention the current sources are controlled by the voltage level which is centered between the mid-potentials of the common mode level differential logic signal and the mid-potential of the differential logic input signal.

Abstract: The configuration described is distinguished by the fact that it contains a control device which ensures that the potential which is established on the current-source side terminal of the switch when the latter is open has the value which it would have if the switch were to be closed, under otherwise unchanged conditions, and if the current output by the current source were to flow through said switch. As a result, it is possible for the current output by the configuration always to be as large as desired, in particular even immediately directly after the closure of the switches P2 and N1, more precisely exactly the current output by the current sources P1 and N2.

Abstract: The configuration described is distinguished by the fact that it contains a control device which ensures that the potential which is established on the current-source side terminal of the switch when the latter is open has the value which it would have if the switch were to be closed, under otherwise unchanged conditions, and if the current output by the current source were to flow through said switch. As a result, it is possible for the current output by the configuration always to be as large as desired, in particular even immediately directly after the closure of the switches P2 and N1, more precisely exactly the current output by the current sources P1 and N2.