Abstract: A circuit arrangement for a reception part of an SDH transmission system for transmitting plesiochronous signals contains input channels assigned to these signals which are connected to a clock synchronizer for the adaptation of the plesiochronous signals to a common processing clock. The clock synchronizer is followed by a multiplexer, to the output of which a reception processor is connected for the transformation of a plesiochronous signal into a synchronous signal for an SDH transmission channel. A circuit arrangement for a transmission part of the SDH transmission system contains a multiplexer, to the output of which a transmission processor is connected for the conversion of a transmitted synchronous signal into a plesiochronous signal. Using a desynchronizer following the transmission processor, the plesiochronous signal clocks are recovered, and the plesiochronous signals are issued to the output channels assigned to them.

Abstract: A voltage-controlled oscillator and a control substitution circuit that interrupts the control loop in case a source of normal control voltage such as a referenced frequency fails, and allows the voltage-controlled oscillator to continue to operate with a nominal control voltage. To allow the oscillator of such a loop to continue to operate for weeks with a practically unchanged frequency under certain circumstances, after the normal control voltage source has failed, the nominal control voltage can be selected such that the oscillator produces an oscillation of a preset frequency. Simultaneously with change-over of the oscillator to the preset frequency, its voltage-to-frequency characteristic is changed by the control substitution circuit such that a change of the control voltage leads to a smaller change in the frequency than in normal operating conditions.