Abstract: A system for the exchange of messages among a multiplicity of processing units includes a data channel and a service line interconnecting respective interfaces of these units. Each interface includes a busy-state detector determining during a test phase of a recurrent time slot whether the service line is available, a logic network connectable in a subsequent acquisition phase the service line in the event of its availability to emit successive bits of an address characterizing the respective processing unit, and a comparator determining during the aquisition phase whether an emitted address bit of a particular logic level ("1") coincides with another bit of a higher-priority level ("0") concurrently sent over the line by some other unit. If a higher-priority address bit is encountered, the emission of the address is aborted and restarted in a subsequent time slot.

Abstract: A line loop designed for the transmission of digitized voice samples as well as data words between an exchange and several subscriber terminals, not all of them necessarily equipped for voice communication, is connected through a modem to a bus with parallel branches extending to all the terminals, each branch including an outgoing-data lead, an incoming-data lead and two ancillary leads carrying clock pulses for the timing of data transmission and reception which are generated at the exchange. Each terminal, identified by a multibit address, is provided with an interface including a carrier sensor which detects the free or busy state of the line--during a time slot assigned to data transmission--on the basis of a certain protocol according to which an idle state is denoted by an unbroken succession of at least seven bits of predetermined logical value (here "1").