Abstract: A median circuit operates over a single-clock-cycle to determine the median of the group. Each value is compared with a plurality of other values. One of those other values become the eventual median. The possible median which is closest to all of the elements being compared is taken as the overall closest value and established as the median. Most specifically, this is done by applying the higher voltage of the pair to one end of a capacitor at the same time as a precharge. After the precharge is complete, the lower voltage of the pair is applied to the capacitor. The capacitor acts as a charge pump, lowering its other end by an amount proportional to the distance between the higher voltage of the pair and the lower voltage of the pair. A plurality of the capacitors are connected together, so that the output from the group of cells represents the average capacitors among all elements. The highest group represents the eventual median.

Abstract: A fully parallel CCD memory chip of N address lines which detects in just one clock cycle, a perfect match between an input pattern and any of a plurality of stored patterns and also detects in less than (N+1)-comparison cycles and still just one XOR operation, the best matching in case a perfect one does not exist. The chip disclosed herein has a fully parallel architecture in which an input word is compared to all stored words at one time. A preferred embodiment of the invention uses a four phase CCD, wherein each stored word occupies one row of the CCD and each such bit of each such word occupies two cells. Where perfect matches exist, only one comparison clock cycle is needed to compare the input word with all stored words and where there is no perfect match, the best match will be detected on a subsequent comparison pulse. Charge packets represent binary words generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines.