Patents by Inventor Volodmyr Shvydun

Volodmyr Shvydun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Receiver with pipelined tap coefficients and shift control
    Patent number: 9294313
    Abstract: A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: March 22, 2016
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Tomasz Prokop, Volodmyr Shvydun, Viswanath Annampedu, Amaresh V. Malipatil
  • RECEIVER WITH PIPELINED TAP COEFFICIENTS AND SHIFT CONTROL
    Publication number: 20150195108
    Abstract: A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.
    Type: Application
    Filed: January 3, 2014
    Publication date: July 9, 2015
    Applicant: LSI Corporation
    Inventors: Tomasz Prokop, Volodmyr Shvydun, Viswanath Annampedu, Amaresh V. Malipatil