Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.

Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.

Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.

Abstract: A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.

Abstract: An electronic system 100 controls power to its central processing unit 22 with digital voltage identification (VID) codes and analog set signals. The VID codes are converted into an analog VID signal by digital to analog converter 42. An analog set voltage 62 generated by a sense network 60 sets the voltage level when the CPU operates at any voltage less than its maximum. Comparator 50 and switch 52 select either the analog VID voltage or the analog set voltage.

Abstract: A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.

Abstract: A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.

Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.

Abstract: A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.