Abstract: A technique for improving multiple critical timing paths that exhibit similar characteristics has been discovered. The technique efficiently improves multiple critical timing paths by reducing the number of unique critical timing path patterns for analysis. In some embodiments of the present invention a method for use in connection with an integrated circuit design includes identifying distinct timing paths of the integrated circuit design. The distinct timing paths have timing violations. The method includes associating a first plurality of the distinct timing paths with a first set of timing paths. Individual ones of the first plurality belonging to a second set of timing paths and include a first common characteristic. The method includes improving the first set of timing paths based at least in part on an improvement to an individual timing path of the first set of timing paths.

Abstract: A technique improves the performance of an integrated circuit design by selectively replacing low Vt transistors with standard Vt transistors. The selection of gates for replacement may be based on a multi-path timing analysis. If a low Vt variant of a gate instance increases a path cycle time as compared to a standard Vt counterpart, the maximum of the path cycle times for all paths that include the low Vt variant and the maximum of the path cycle time for these paths with a standard Vt variant are calculated. If the maximum path cycle time for the path including the low Vt variant is greater than the maximum path cycle time for the path including the standard Vt variant, then that low Vt variant is substituted with a standard Vt variant. Thus, integrated circuit designs prepared in accordance with the invention may exhibit improved cycle times.

Abstract: Method and system for providing a netlist driven integrated router in a non-netlist driven environment for microprocessor designs includes retrieving top level netlist for the existing microprocessor design from the top level database and the design parameters for the new microprocessor design, and translating these netlist and design parameters at the front end so that the resulting data can be provided to an integrated router which is configured to generate re-routes for the new microprocessor design based on the top level netlist and the design parameters, where the generated re-routes are provided to a back end for translating the re-routes to new top level netlist and merging the new top level netlist with the existing top level netlist database.

Abstract: Method and system for providing a netlist driven integrated router in a non-netlist driven environment for microprocessor designs includes retrieving top level netlist for the existing microprocessor design from the top level database and the design parameters for the new microprocessor design, and translating these netlist and design parameters at the front end so that the resulting data can be provided to an integrated router which is configured to generate re-routes for the new microprocessor design based on the top level netlist and the design parameters, where the generated re-routes are provided to a back end for translating the re-routes to new top level netlist and merging the new top level netlist with the existing top level netlist database.