Abstract: A data processing system is disclosed in which memory modules are connected at ports of interconnecting buses, with the physical addresses of the modules not necessarily being contiguous. The system includes a random access memory for translating contiguous logical memory addresses, as generated by a processor, to the physical addresses of the memory modules. The operation of the random access memory is such that memory modules of various sizes can be used together. Switching is provided for selectively interchanging word address bits and module address bits before the transformation is performed by the random access memory, thereby providing interleaving.