Patents by Inventor Vrinda Achuthan PADMAKUMARI

Vrinda Achuthan PADMAKUMARI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PROCESS TO RELAY KNOWLEDGE AND GUIDE SYNTHESIS ALONGSIDE EARLY DETECTION OF LOGIC OPTIMIZATIONS
    Publication number: 20240046014
    Abstract: A method for verifying an electronic circuit design includes detecting a first issue in a register transfer level description of the electronic circuit design and receiving a selection to waive the first issue. The method also includes capturing the selection to waive the first issue in a memory, detecting, by a processing device, a second issue while generating a netlist or gate level description of the electronic circuit design, and based on determining that the selection to waive the first issue indicated in the memory applies to the second issue, suppressing or ignoring the second issue.
    Type: Application
    Filed: November 29, 2022
    Publication date: February 8, 2024
    Inventors: Himanshu KATHURIA, Rohit Kumar OHLAYAN, Paras Mal JAIN, Vrinda Achuthan PADMAKUMARI, Harpreet Singh ANAND, Ila VERMA, Priya NAYAK, Suresh Babu BARLA, Judy SZE