Abstract: Aspects of the subject disclosure may include, for example, a porous electrode that includes a porous layer, and a pattern of flow channels defined in the porous layer, wherein a first flow channel in the pattern of flow channels has a shape that at least partially approximates a cube-root profile. Additional embodiments are disclosed.

Abstract: The present disclosure provides a vertical tunneling random access memory comprising: a first electrode disposed on a base substrate; a second electrode vertically spaced from the first electrode; a floating gate disposed between the first electrode and the second electrode and configured to charge or discharge charges; a tunneling insulating layer disposed between the first electrode and the floating gate; a barrier insulating layer disposed between the floating gate and the second electrode; a contact hole passing through the tunneling insulating layer and the barrier insulating layer for partially exposing the first electrode; a semiconductor pattern extending from the second electrode, along and on a portion of a side wall face defining the contact hole, to the first electrode such that one end of the semiconductor pattern is in contact with the first electrode and the other end of the pattern is in contact with the second electrode.

Abstract: The present disclosure provides a vertical tunneling random access memory comprising: a first electrode disposed on a base substrate; a second electrode vertically spaced from the first electrode; a floating gate disposed between the first electrode and the second electrode and configured to charge or discharge charges; a tunneling insulating layer disposed between the first electrode and the floating gate; a barrier insulating layer disposed between the floating gate and the second electrode; a contact hole passing through the tunneling insulating layer and the barrier insulating layer for partially exposing the first electrode; a semiconductor pattern extending from the second electrode, along and on a portion of a side wall face defining the contact hole, to the first electrode such that one end of the semiconductor pattern is in contact with the first electrode and the other end of the pattern is in contact with the second electrode.

Abstract: An infant towel drying mat that is intended to provide a convenient and effective apparatus to aid in the drying of a human infant or a pet animal. A drying mat has a first section, a second section, and a section hinge, wherein the first section and the second hinge are adjacently connected to the section hinge; the section hinge being positioned in between the first section and the second section and allows for multiple configurations of the infant towel drying mat. A plurality of connection tabs is adjacently connected to the drying mat and perimetrically positioned around the drying mat. Each of the plurality of connection tabs includes a protrusion connected to the drying mat, a surface fastener to be secured to a surface, and a press towel holder for mounting a towel. The surface fastener and the press towel holder are positioned opposite each other about the protrusion.

Abstract: An infant towel drying mat that is intended to provide a convenient and effective apparatus to aid in the drying of a human infant or a pet animal. A drying mat has a first section, a second section, and a section hinge, wherein the first section and the second hinge are adjacently connected to the section hinge; the section hinge being positioned in between the first section and the second section and allows for multiple configurations of the infant towel drying mat. A plurality of connection tabs is adjacently connected to the drying mat and perimetrically positioned around the drying mat. Each of the plurality of connection tabs includes a protrusion connected to the drying mat, a surface fastener to be secured to a surface, and a press towel holder for mounting a towel. The surface fastener and the press towel holder are positioned opposite each other about the protrusion.

Abstract: In methods for making interconnect structures for semiconductor devices a layer of seed material is formed on a first substantially planar dielectric layer which covers the semiconductor devices at predetermined locations where interconnect conductor is desired, a second substantially planar dielectric insulating layer is formed over the first substantially planar dielectric insulating layer and the seed material, the second layer having openings extending therethrough at the predetermined locations to expose at least a portion of the seed material, and conductive material is selectively deposited on the exposed seed material to fill the openings. The seed material may be a material in the group consisting of aluminum alloys, refractory metals and metal silicides, or may be SiO.sub.2 selectively implanted with silicon ions. The insulating material may be SiO.sub.2.