Abstract: A system for error reporting and handling includes a memory storing an error handler, a processor configured to execute the error handler, and a buffer. The error handler is configured to receive an error message from a system on chip (SOC) platform. The error message indicates a plurality of errors have occurred in the SOC platform, and the buffer stores the error message. Further, the error handler is configured to report the error message using a single interrupt. Further, the error handler is configured to handle the errors in the error message using the single interrupt.

Abstract: A system for error reporting and handling includes a memory storing an error handler, a processor configured to execute the error handler, and a buffer. The error handler is configured to receive an error message from a system on chip (SOC) platform. The error message indicates a plurality of errors have occurred in the SOC platform, and the buffer stores the error message. Further, the error handler is configured to report the error message using a single interrupt. Further, the error handler is configured to handle the errors in the error message using the single interrupt.

Abstract: A system and method for executing instructions in a constrained order. In some embodiments, the method includes: sending by a host, a first instruction, followed by an order-constrained instruction, followed by a second instruction; receiving, by a target, the first instructions, the order-constrained instruction, and the second instruction; and executing, by the target, the first instruction; the order-constrained instruction, after executing the first instruction; and the second instruction, after executing the order-constrained instruction.

Abstract: A system and method for executing instructions in a constrained order. In some embodiments, the method includes: sending by a host, a first instruction, followed by an order-constrained instruction, followed by a second instruction; receiving, by a target, the first instructions, the order-constrained instruction, and the second instruction; and executing, by the target, the first instruction; the order-constrained instruction, after executing the first instruction; and the second instruction, after executing the order-constrained instruction.

Abstract: A solid state storage device including a non-volatile memory Express (NVMe) controller and configured to manage a Host Memory Buffer (HMB) in a host may be provided. The NVMe controller may be configured to fetch HMB descriptor entries as part of a feature command from the host, partition the HMB logically into a control buffer partition and a data buffer partition, store the HMB descriptor entries pointing to the control buffer partition within the solid state storage device as an HMB pointer list table, and write-back the HMB descriptor entries pointing to the data buffer partition into the control buffer partition of HMB.

Abstract: A solid state storage device including a non-volatile memory Express (NVMe) controller and configured to manage a Host Memory Buffer (HMB) in a host may be provided. The NVMe controller may be configured to fetch HMB descriptor entries as part of a feature command from the host, partition the HMB logically into a control buffer partition and a data buffer partition, store the HMB descriptor entries pointing to the control buffer partition within the solid state storage device as an HMB pointer list table, and write-back the HMB descriptor entries pointing to the data buffer partition into the control buffer partition of HMB.