Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

Abstract: The present disclosure relates to a semiconductor device including a substrate, a first region disposed in the substrate, a terminal region disposed in the first region, a body contact region disposed in the first region and spaced apart from the terminal region, a dielectric layer disposed on the substrate over the first region between the terminal region and the body contact region, an electrically conductive layer disposed on the dielectric layer, and a continuous metallic layer disposed on the electrically conductive layer and extending to the body contact region, the continuous metallic layer disposed on the body contact region and in physical contact with a top and side portions of the electrically conductive layer. The semiconductor device may additionally include a body contact interconnect disposed on a portion of the continuous metallic layer over the electrically conductive layer.

Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

Abstract: A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.

Abstract: A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.

Abstract: A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.

Abstract: A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.

Abstract: Electronic devices and methods of producing such electronic devices are provided. In an exemplary embodiment, a method of producing an electronic device includes forming a protected circuit and an ESD circuit, where the ESD circuit is configured to discharge an electrostatic discharge (ESD) to a ground such that the ESD bypasses the protected circuit. An ESD transistor is formed in the ESD circuit, where the ESD transistor includes a source and a drain. The ESD transistor also includes a gate with a gate width perpendicular to a gate length, where the gate length is measured across the gate from the source to the drain. A trigger voltage of the ESD transistor is set by adjusting the gate width.

Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a deep well with a drain well overlying the deep well. A first source well also overlies the deep well, where the first source well includes a first source well concentration of conductivity determining impurities. A second source well overlies the first source well, where the second source well includes a second concentration of conductivity determining impurities that is higher than the first source well concentration. A drain overlies the drain well and a source overlies the second source well. A channel is defined between the source and the drain and a gate overlies the channel.