Abstract: A transistor storage for entering and storing information in and simultaneously reading information from two columns of a matrix of memory cells with different addresses. The transistor storage comprises two multidigit data buses connected to the columns of the memory cell matrix. Each memory cell of the matrix comprises a storage element and two induced channel transistors connected to the storage element and to the multidigit data buses. The multidigit data buses are connected to write circuits and read amplifiers of a first readout direction and second readout direction, which are connected to an input multidigit data bus and an output multidigit data bus. The write circuits are connected to write and read buses. The read amplifiers are connected to the read bus.

Abstract: A microcomputer processor comprises a scratch-pad storage, an arithmetic-logical unit, an interface unit and a microprogram unit, all interconnected by means of an intraprocessor data bus, and a processor status register. The processor further comprises a constant file, first and second switching elements connected to the arithmetic-logical unit, a register, a source of logic potentials and a decoder. The present invention helps increase the speed of microcomputer processor and expand its functional capabilities.

Abstract: Microprocessor apparatus for data exchange is controlled by information supplied via a microinstruction bus and a triggering line and transmits data from some external bidirectional data buses to other such buses. Data is supplied via data exchange units (1.sub.1, 1.sub.2, 2), internal bidirectional data buses and a switch. In addition to the transmission of information, the microprocessor apparatus can, depending on the code of the microinstruction, count the number of transmitted words via a counter and compare or mask data or arbitrate transmitted data via a data processing/converting unit. While executing microinstructions, the counter, the data processing unit, a register unit and a switch shape distinguishing features of the processed information, to be later fed to a conditional operation unit. The conditional operation unit shapes a generalized condition for readjustment of operation of a control unit.

Abstract: A data processing system intended for handling multiple tasks and comprising at least two processors, a memory unit and an I/O unit which are all connected to a data address and control signal transmission line. Each of the processors comprises an arithmetic-logic unit, a scratch pad memory, a processor status register, an interface, and a control unit which are all interconnected by a processor data bus. Each of the processors further contains an address interrupt unit whose input/output is connected to the data address and control signal transmission line. A first output of the address interrupt unit is connected to the processor data bus and its second output is connected to a second input of the control unit. A second control output of the control unit is connected to the input of the address interrupt unit. The invention helps increase the throughput of a data processing system and simplify the programming of interaction between the system's processors.

Abstract: According to the invention, a microprocessor computing system comprises at least one data processing device and at least one group of execution control elements; said group constitutes a control level and includes at least one microprogram control device which is a group of first-order control elements. The data processing device incorporates a microinstruction register for holding microinstruction codes, a microoperation decoder, a general-purpose register unit for holding operands, an arithmetic/logic unit, a temporary result storage register, a result status register, and at least one data exchange unit having a multichannel communication line to provide for data exchange between other sources and destinations. The microprogram control device producing parallel microinstruction codes incorporates at least one input register, a programmable address unit, a microinstruction storage unit, a feedback register, a microinstruction register, and an output driver unit.