Patents by Inventor Vyacheslav Vladimirovich MALYUGIN
Vyacheslav Vladimirovich MALYUGIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11507477Abstract: System and method for providing fault tolerance in virtualized computer systems use a first guest and a second guest running on virtualization software to produce outputs, which are produced when a workload is executed on the first and second guests. An output of the second guest is compared with an output of the first guest to determine if there is an output match. If there is no output match, the first guest is paused and a resynchronization of the second guest is executed to restore a checkpointed state of the first guest on the second guest. After the resynchronization of the second guest, the paused first guest is caused to resume operation.Type: GrantFiled: February 25, 2020Date of Patent: November 22, 2022Assignee: VMware, Inc.Inventors: Ganesh Venkitachalam, Rohit Jain, Boris Weissman, Daniel J. Scales, Vyacheslav Vladimirovich Malyugin, Jeffrey W. Sheldon, Min Xu
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Publication number: 20200192771Abstract: System and method for providing fault tolerance in virtualized computer systems use a first guest and a second guest running on virtualization software to produce outputs, which are produced when a workload is executed on the first and second guests. An output of the second guest is compared with an output of the first guest to determine if there is an output match. If there is no output match, the first guest is paused and a resynchronization of the second guest is executed to restore a checkpointed state of the first guest on the second guest. After the resynchronization of the second guest, the paused first guest is caused to resume operation.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Inventors: Ganesh Venkitachalam, Rohit Jain, Boris Weissman, Daniel J. Scales, Vyacheslav Vladimirovich Malyugin, Jeffrey W. Sheldon, Min Xu
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Patent number: 10579485Abstract: In a computer system running at least a first virtual machine (VM) and a second VM on virtualization software, a computer implemented method for the second VM to provide quasi-lockstep fault tolerance for the first VM includes executing a workload on the first VM and the second VM that involves producing at least one externally visible output and comparing an externally visible output of the second VM with an externally visible output of the first VM to determine if there is an output match. In response to a determination that the externally visible output of the second VM does not match the externally visible output of the first VM, a resynchronization of the second VM is executed. The externally visible output of the first VM is kept from being output externally until completion of the resynchronization.Type: GrantFiled: October 3, 2016Date of Patent: March 3, 2020Assignee: VMWARE, INC.Inventors: Ganesh Venkitachalam, Rohit Jain, Boris Weissman, Daniel J. Scales, Vyacheslav Vladimirovich Malyugin, Jeffrey W. Sheldon, Min Xu
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Patent number: 10474385Abstract: Systems, devices, and methods for managing fragmentation in hardware-assisted compression of data in physical computer memory which may result in reduced internal fragmentation. An example computer-implemented method comprises: providing, by a memory management program to compression hardware, a compression command including an address in physical computer memory of data to be compressed and a list of at least two available buffers for storing compressed data; using, by the compression hardware, the address included in the compression command to retrieve uncompressed data; compressing the uncompressed data; and selecting, by the compression hardware, from the list of at least two available buffers, at least two buffers for storing compressed data based on an amount of space that would remain if the compressed data were stored in the at least two buffers, wherein each of the at least two selected buffers differs in size from at least one other of the selected buffers.Type: GrantFiled: December 29, 2016Date of Patent: November 12, 2019Assignee: Google LLCInventors: Santhosh Rao, Sameer Nanda, Vyacheslav Vladimirovich Malyugin, Luigi Semenzato, Aaron Durbin, Keith Robert Pflederer, Hsiao-Heng Kelin Lee, Rahul Jagdish Thakur
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Patent number: 10089239Abstract: Provided are methods, systems, and apparatus for managing and controlling memory caches, in particular, system level caches outside of those closest to the CPU. The processes and representative hardware structures that implement the processes are designed to allow for detailed control over the behavior of such system level caches. Caching policies are developed based on policy identifiers, where a policy identifier corresponds to a collection of parameters that control the behavior of a set of cache management structures. For a given cache, one policy identifier is stored in each line of the cache.Type: GrantFiled: May 26, 2016Date of Patent: October 2, 2018Assignee: Google LLCInventors: Allan D. Knies, Shinye Shiu, Chih-Chung Chang, Vyacheslav Vladimirovich Malyugin, Santhosh Rao
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Patent number: 9928180Abstract: The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.Type: GrantFiled: February 20, 2017Date of Patent: March 27, 2018Assignee: VMware, Inc.Inventors: Vyacheslav Vladimirovich Malyugin, Boris Weissman, Ganesh Venkitachalam, Min Xu
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Patent number: 9864541Abstract: Provided are methods and systems for memory decompression using a hardware decompressor that minimizes or eliminates the involvement of software. Custom decompression hardware is added to the memory subsystem, where the decompression hardware handles read accesses caused by, for example, cache misses or requests from devices to compressed memory blocks, by reading a compressed block, decompressing it into an internal buffer, and returning the requested portion of the block. The custom hardware is designed to determine if the block is compressed, and determine the parameters of compression, by checking unused high bits of the physical address of the access. This allows compression to be implemented without additional metadata, because the necessary metadata can be stored in unused bits in the existing page table structures.Type: GrantFiled: February 12, 2016Date of Patent: January 9, 2018Assignee: Google LLCInventors: Vyacheslav Vladimirovich Malyugin, Luigi Semenzato, Choon Ping Chng, Santhosh Rao, Shinye Shiu
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Publication number: 20170242614Abstract: Systems, devices, and methods for managing fragmentation in hardware-assisted compression of data in physical computer memory which may result in reduced internal fragmentation. An example computer-implemented method comprises: providing, by a memory management program to compression hardware, a compression command including an address in physical computer memory of data to be compressed and a list of at least two available buffers for storing compressed data; using, by the compression hardware, the address included in the compression command to retrieve uncompressed data; compressing the uncompressed data; and selecting, by the compression hardware, from the list of at least two available buffers, at least two buffers for storing compressed data based on an amount of space that would remain if the compressed data were stored in the at least two buffers, wherein each of the at least two selected buffers differs in size from at least one other of the selected buffers.Type: ApplicationFiled: December 29, 2016Publication date: August 24, 2017Applicant: GOOGLE INC.Inventors: Santhosh RAO, Sameer NANDA, Vyacheslav Vladimirovich MALYUGIN, Luigi SEMENZATO, Aaron DURBIN, Keith Robert PFLEDERER, Hsiao-Heng Kelin LEE, Rahul Jagdish THAKUR
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Publication number: 20170228320Abstract: The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.Type: ApplicationFiled: February 20, 2017Publication date: August 10, 2017Inventors: Vyacheslav Vladimirovich MALYUGIN, Boris WEISSMAN, Ganesh VENKITACHALAM, Min XU
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Patent number: 9575899Abstract: The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.Type: GrantFiled: November 30, 2015Date of Patent: February 21, 2017Assignee: VMware, Inc.Inventors: Vyacheslav Vladimirovich Malyugin, Boris Weissman, Ganesh Venkitachalam, Min Xu
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Publication number: 20170024291Abstract: In a computer system running at least a first virtual machine (VM) and a second VM on virtualization software, a computer implemented method for the second VM to provide quasi-lockstep fault tolerance for the first VM includes executing a workload on the first VM and the second VM that involves producing at least one externally visible output and comparing an externally visible output of the second VM with an externally visible output of the first VM to determine if there is an output match. In response to a determination that the externally visible output of the second VM does not match the externally visible output of the first VM, a resynchronization of the second VM is executed. The externally visible output of the first VM is kept from being output externally until completion of the resynchronization.Type: ApplicationFiled: October 3, 2016Publication date: January 26, 2017Applicant: VMware, Inc.Inventors: Ganesh Venkitachalam, Rohit Jain, Boris Weissman, Daniel J. Scales, Vyacheslav Vladimirovich Malyugin, Jeffrey W. Sheldon, Min Xu
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Publication number: 20160350232Abstract: Provided are methods, systems, and apparatus for managing and controlling memory caches, in particular, system level caches outside of those closest to the CPU. The processes and representative hardware structures that implement the processes are designed to allow for detailed control over the behavior of such system level caches. Caching policies are developed based on policy identifiers, where a policy identifier corresponds to a collection of parameters that control the behavior of a set of cache management structures. For a given cache, one policy identifier is stored in each line of the cache.Type: ApplicationFiled: May 26, 2016Publication date: December 1, 2016Applicant: GOOGLE INC.Inventors: Allan D. KNIES, Shinye SHIU, Chih-Chung CHANG, Vyacheslav Vladimirovich MALYUGIN, Santhosh RAO
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Publication number: 20160239209Abstract: Provided are methods and systems for memory decompression using a hardware decompressor that minimizes or eliminates the involvement of software. Custom decompression hardware is added to the memory subsystem, where the decompression hardware handles read accesses caused by, for example, cache misses or requests from devices to compressed memory blocks, by reading a compressed block, decompressing it into an internal buffer, and returning the requested portion of the block. The custom hardware is designed to determine if the block is compressed, and determine the parameters of compression, by checking unused high bits of the physical address of the access. This allows compression to be implemented without additional metadata, because the necessary metadata can be stored in unused bits in the existing page table structures.Type: ApplicationFiled: February 12, 2016Publication date: August 18, 2016Applicant: GOOGLE INC.Inventors: Vyacheslav Vladimirovich MALYUGIN, Luigi SEMENZATO, Choon Ping CHNG, Santhosh RAO, Shinye SHIU
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Publication number: 20160085686Abstract: The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.Type: ApplicationFiled: November 30, 2015Publication date: March 24, 2016Inventors: Vyacheslav Vladimirovich MALYUGIN, Boris WEISSMAN, Ganesh VENKITACHALAM, Min XU
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Patent number: 9213651Abstract: The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.Type: GrantFiled: June 16, 2009Date of Patent: December 15, 2015Assignee: VMware, Inc.Inventors: Vyacheslav Vladimirovich Malyugin, Boris Weissman, Ganesh Venkitachalam, Min Xu
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Publication number: 20100318762Abstract: The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.Type: ApplicationFiled: June 16, 2009Publication date: December 16, 2010Applicant: VMWARE, INC.Inventors: Vyacheslav Vladimirovich MALYUGIN, Boris WEISSMAN, Ganesh VENKITACHALAM, Min XU