Abstract: An integrated injection circuit is proposed which comprises a current generator and a normally cutoff n-channel field-effect transistor. The gate of the FET is connected to the current generator and to the input electrode of the circuit, the source is grounded and the drain is connected to the output electrode of the circuit. The gate of the FET is designed as at least one non-injecting rectifying contact.

Abstract: A data processing device for variable length formats includes a control unit and a storage unit coupled to the control unit. Two data exchange buses are each coupled to a respective data input and to a respective data output of the storage unit. Two switches are coupled to the control unit and to respective data exchange buses. An arithmetic/logic unit is coupled to the control unit, to the switches and to the storage unit. A data shaft unit is coupled to the data exchange buses and to the control unit. A data masking unit is coupled to the data exchange buses, to the control unit and to the switches. This device enables the preparation for processing of multibyte data fields arbitrarily arranged with respect to the word boundaries in main storage. The data shift unit provides automatic alignment of the bytes of the operands relative to each other. The data masking unit masks irrelevant bytes of the first and last words of each operand.

Abstract: The integrated logic circuit of the invention comprises a switching field-effect transistor and a current source, which is another field-effect transistor having its conductivity complementary to that of the switching field-effect transistor. The second field-effect transistor has its gate coupled to the source of the switching field-effect transistor, and to an electrode of a power supply its source coupled to the other power supply circuit electrode and its drain coupled to the gate of the switching field-effect transistor. The gate and the drain of the switching field-effect transistor are respectively connected to the input and the output of the circuit.

Abstract: An integrated injection logic circuit comprises a switching element using a unipolar FET whose gates are connected to the collectors of a load transistor. The emitter of the load transistor is connected to a power supply and the base area is combined with the source of the unipolar FET and grounded. Connected to the gates of the unipolar FET and to the base area of the load transistor are double-pole gating elements. The number of such elements is equal to the number of gates of the unipolar FET. The conduction voltage of the gating elements is lower than that across the p-n junctions of the respective gates of the unipolar FET.

Abstract: The proposed information selection device includes an initial address register and a memory address forming unit. The forming unit is electrically connected to two coincidence circuits, a functional return address jump register and a control information decoder. The control information decoder is connected to a memory unit for storing control information. A constant register connected to the functional return address jump register. A control information register is connected to the control information decoder. The control information decoder is connected to each of the coincidence circuits. An analysis signal register is connected to an analysis signal forming decoder. A comparison code register and a comparison mask register are also included. To both coincidence circuits there is connected a comparison unit for comparing information, which is being analyzed, with a respective code.

Abstract: Disclosure is made of a method for dividing two numbers, whereby the numbers are converted to the binary code, and there is formed an address code of three digits of the dividend (the or remainder) by determining the position of the highest-order significant digit in the three high-order digits of the divisor. The address thus formed serves to produce three digits of the remainder, i.e. a digit corresponding to the highest-order significant digit of the divisor code and two adjacent higher-order digits. The three digits of the remainder are analyzed and, depending upon the result of the analysis, the code of either the single, or doubled, or trebled divisor is subtracted from the remainder code, whereby the next two quotient code digits are produced.Disclosure is further made of a device for effecting the proposed method for dividing two numbers, which comprises an arithmetic unit connected to dividend (or remainder) registers, buffer registers, divisor registers and quotient registers.