Patents by Inventor Vyankatesh Gupta

Vyankatesh Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for eliminating bit disturbance errors in non-volatile memory devices
    Patent number: 11327882
    Abstract: A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: May 10, 2022
    Assignee: Allegro MicroSystems, LLC
    Inventors: Muhammed Sarwar, Vyankatesh Gupta, James McClay, Sundar Chetlur, Harianto Wong, Gerardo A. Monreal, Nicolás Rafael Biberidis, Octavio H. Alpago, Nicolas Rigoni
  • Method and apparatus for eliminating EEPROM bit-disturb
    Patent number: 11170858
    Abstract: A method for use in a memory device including a first memory matrix is provided, the method comprising: receiving a write request that is associated with a first memory cell, the first memory cell being part of the first memory matrix; copying a content of a second memory cell into a register, the second memory cell being part of the first memory matrix; overwriting the second memory cell with the content of the register when the content of the second memory cell is different from the content of the register; and writing, to the first memory cell, at least a portion of data that is associated with the write request.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: November 9, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Muhammad Sarwar, Vyankatesh Gupta, James McClay, Sundar Chetlur, Harianto Wong
  • METHOD AND APPARATUS FOR ELIMINATING EEPROM BIT-DISTURB
    Publication number: 20210295932
    Abstract: A method for use in a memory device including a first memory matrix is provided, the method comprising: receiving a write request that is associated with a first memory cell, the first memory cell being part of the first memory matrix; copying a content of a second memory cell into a register, the second memory cell being part of the first memory matrix; overwriting the second memory cell with the content of the register when the content of the second memory cell is different from the content of the register; and writing, to the first memory cell, at least a portion of data that is associated with the write request.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 23, 2021
    Applicant: Allegro MicroSystems, LLC
    Inventors: Muhammad Sarwar, Vyankatesh Gupta, James McClay, Sundar Chetlur, Harianto Wong
  • METHOD AND APPARATUS FOR ELIMINATING BIT DISTURBANCE ERRORS IN NON-VOLATILE MEMORY DEVICES
    Publication number: 20210240606
    Abstract: A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 5, 2021
    Applicant: Allegro MicroSystems, LLC
    Inventors: Muhammed Sarwar, Vyankatesh Gupta, James McClay, Sundar Chetlur, Harianto Wong, Gerardo A. Monreal, Nicolás Rafael Biberidis, Octavio H. Alpago, Nicolas Rigoni