Abstract: Hybrid fiber/coax networks employ the existing cable plant used for cable TV and transmit data signals in a frequency bandwidth above that which is used for cable TV. As this cable plant was deployed in a tree and branch topology, data transmissions may be susceptible to noise, variable transmission loss and frequency dispersion, particularly in the upstream direction. Further, due to the tree and branch topology, homes at the far end of the network experience much greater loss than do the homes that are near to the headend/ONU. The present system, which uses point-to-point data links between intelligent network elements located in the feeder/distribution network to provide reliable, secure, bi-directional broadband access. Digital signals are terminated at the intelligent network elements, switched and regenerated for transmission across additional upstream or downstream data links as needed to connect a home to a headend or router.

Abstract: Hybrid fiber/coax networks employ the existing cable plant used for cable TV and transmit data signals in a frequency bandwidth above that which is used for cable TV. As this cable plant was deployed in a tree and branch topology, data transmissions may be susceptible to noise, variable transmission loss and frequency dispersion, particularly in the upstream direction. Further, due to the tree and branch topology, homes at the far end of the network experience much greater loss than do the homes that are near to the headend/ONU. The present system, which uses point-to-point data links between intelligent network elements located in the feeder/distribution network to provide reliable, secure, bi-directional broadband access. Digital signals are terminated at the intelligent network elements, switched and regenerated for transmission across additional upstream or downstream data links as needed to connect a home to a headend or router.

Abstract: A central processing unit (CPU) 10 comprises an external control memory for storing microinstructions which correspond to macroinstructions read from a system memory. The microinstructions are 56 bits in length and are read in 28-bit segments. CPU 10 also comprises an internal memory management unit (MMU) 18 which comprises a plurality of address translation entry (ATE) registers four of which are permanent and sixteen of which are temporary in that the storage of a new translation entry occurs in a least recently used temporary translation entry register. CPU 10 also comprises a plurality of status register bits, some of which are settable only by predefined microinstructions. All of the status register bits are branchable. CPU 10 further comprises a condition code register the state of which may be determined by input signal pins. CPU 10 also comprises address generation logic which may generate a 24, 31 or 32 bit address upon a 32-bit address bus.