Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width wmux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width wmux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.

Abstract: A programmable logic device includes a node and a RAM cell configured to power-up in a preferred state so as to provide a predetermined logic signal to the node upon power-up. The node may comprise an interconnection element, for example a transistor. Associated with the interconnection element may be two signal lines within the programmable logic device, for example, as part of a programmable interconnect matrix. The interconnection element and the two signal lines are associated such that when the interconnection element is in a first state the two signal lines are electrically coupled and when the interconnection element is in a second state the two signal lines are not electrically coupled. The predetermined logic signal from the RAM cell selects one of the first and second states. The RAM cell may include two PMOS transistors, each having an associated threshold voltage, wherein the threshold voltage of one of the PMOS transistors is lower than the threshold voltage of the other PMOS transistor.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuitry for synchronizing the asynchronous logic derived clock signal to be a reference clock signal is coupled to the circuitry for generating. The circuitry for synchronizing generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal but only when the input signals are recognized as clocking signals. That is, the synchronizing circuitry discriminates between valid input signals and spurious signals or noise. Further, the programmable device includes circuitry for suspending a clock signal. In one embodiment, input signal having at least a minimum duration is received and used to generate an asynchronous logic derived clock signal.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a plurality of input signals. Circuitry for synchronizing the asynchronous logic derived clock signal to a reference clock signal is coupled to the circuitry for generating. The circuitry for synchronizing generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal is produced only when the input signals from which the asynchronous logic derived clock signal is created are recognized as proper input signals and the synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input signals. Spurious input signals or noise are rejected.

Abstract: A programmable device includes means for generating an asynchronous logic derived clock signal from one or more of a plurality input signals. Means for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the means for generating the asynchronous logic derived clock signal. The means for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal.

Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.

Abstract: A programmable device includes a circuit for generating an asynchronous logic derived clock signal derived from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating the asynchronous logic derived clock signal. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous clock signal and a reference clock signal. The programmable device further includes a circuit for suspending a clock signal. In one embodiment, a logic derived clock signal is generated and synchronized with a synchronous clock signal. In synchronizing the logic derived clock signal an intermediate signal is generated during a first clock cycle of the synchronous clock signal and is combined with the synchronized logic derived clock signal during a second clock cycle of the synchronous clock signal to produce a suspendable clock signal.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to be a reference clock signal are coupled to the circuitry for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal but only when the input signals are recognized as clocking signals. That is, the synchronizing circuits discriminate between valid input signals and spurious signals or noise.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a plurality of input signals. Further circuitry for synchronizing the asynchronous logic derived clock signal to a reference clock signal is coupled to the generating circuitry. The synchronizing circuit generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal is produced only when the input signals from which the asynchronous logic derived clock signal is created are recognized as proper input signals and the synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input signals. Spurious input signals or noise are rejected.

Abstract: A programmable device includes means for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Means for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the means for generating. The means for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input logic signals from which the synchronized logic derived clock signal is created.

Abstract: A programmable device includes a circuit for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input logic signals from which the synchronized logic derived clock signal is created. Further, the programmable device includes circuit for suspending a clock signal. In one embodiment, an asynchronous logic derived clock signal is generated and synchronized with a synchronous clock signal provided to the programmable device to produce a synchronized logic derived clock signal.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: An asynchronous anticontention circuit for a bi-directional bus. The asynchronous anticontention circuit comprises an anticontention circuit coupled to an asynchronous delay circuit. The anticontention circuit receives a driver select signal and generates a first signal and a second signal. The first signal and the second signal each have an active state and an inactive state. When the driver select signal is in a first logic state, the first signal is in the inactive state and the second signal is in the active state. When the driver select signal transitions from the first logic state to a second logic state, the anticontention circuit transitions the second signal from the active state to the inactive state. The asynchronous delay circuit couples the transition of the second signal to the anticontention circuit after a delay of time. After the delay of time, the anticontention circuit transitions the first signal from the inactive state to the active state.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: A synchronous contention prevention circuit for a bi-directional bus. The synchronous contention prevention circuit comprises a synchronous anticontention circuit coupled to a first input/output circuit. The synchronous anticontention circuit receives a driver select signal and a clock signal. The first input/output circuit has a first input coupled to the synchronous anticontention circuit and a first output. When the driver select signal is in a first logic state, the first input/output circuit is disabled from driving the first output. Subsequently, the driver select signal transitions from the first logic state to a second logic state. After the driver select signal transition to the second logic state, the synchronous anticontention circuit generates a first signal in response to a first transition of the clock signal. The synchronous anticontention circuit then generates a second signal in response to the first signal and a second transition of the clock signal.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.