Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate remove to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.

Abstract: A method for interconnecting stacked layers containing integrated circuit die and a device built from the method is disclosed. The stacked layers are bonded together to form a module whereby individual I/O pads of the integrated circuit die are rerouted to at least one edge of the module. The rerouted leads terminate at the edge. Channels are formed in a surface of the module or on the surface of a layer whereby the rerouted leads are disposed within the channel. The entire surface of the edge or layer is metalized and a predetermined portion of the metalization removed such that the rerouted leads within each channel are electrically connected to each other.

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: Different web pages on a web server are associated with different qualification profiles, each of which is assigned a value by the web-site proprietor. Traffic data hits at the web-site are analyzed to determine which web pages the visitor viewed on the web server. Each qualifying visitor is thereafter associated with a qualification profile and a corresponding value. In another aspect of the invention, visitors arriving as a result of an advertisement on a remote web-site are tracked. The web-site proprietor is consequently able to determine a return on advertising investment based on the value of visitors brought to the site by the tracked advertisement.

Abstract: Different web pages on a web server are associated with different qualification profiles, each of which is assigned a value by the web-site proprietor. Traffic data hits at the web-site are analyzed to determine which web pages the visitor viewed on the web server. Each qualifying visitor is thereafter associated with a qualification profile and a corresponding value. In another aspect of the invention, visitors arriving as a result of an advertisement on a remote web-site are tracked. The web-site proprietor is consequently able to determine a return on advertising investment based on the value of visitors brought to the site by the tracked advertisement.

Abstract: A plurality of temperature dependent focal plane arrays operate without a temperature stabilization cooler and/or heater over a wide range of ambient temperatures. Gain, offset and/or bias correction tables are provided in a flash memory in memory pages indexed by the measured temperature of the focal plane arrays. The memory stores a calibration database, which is accessed using a logic circuit which generates a memory page address from a digitized temperature measurement of each of the focal plane array. The calibration database is comprised of an array of bias, gain and offset values for each pixel in the focal plane array for each potential operating temperature over the entire range of potential operating temperatures. The bias, gain and offset data within the database are read out, converted to analog form, and used by analog circuits to correct the focal plane array response.