Abstract: In an embodiment, during an overload or short circuit condition, a current limit circuit of an inverter is utilized in a pulse-by-pulse manner, which in turn causes the AC output of the inverter to operate in a hiccup mode (e.g., pulse-by-pulse based on and off dependent upon the output current) and automatically recover once the operating parameters (e.g., output current) are within the proper ranges. The pulse-by-pulse current limit circuit is configured to protect the switching circuits of the inverter from shorting or device failure during any peak operating voltage conditions by ensuring on/off timing accuracy of the inverter.

Abstract: A voltage transient protection utilizes Zener diodes, resisters, and a power MOSFET to clamp down the DC spike or surged voltage at the input and prevent damage to the inverter's DC power and control section. The input reverse polarity protection utilizes blocking diodes and a switch to cut off reverse voltage and prevent damage to the DC power and control section of the inverter. Once the surge voltage and/or reverse voltage conditions have been removed, the inverter will automatically recover and power on. In addition, an AC output interlock protection circuit is in place to provide safety protection to the external load. The AC output interlock protection circuit utilizes interlock jumpers on the mating connectors, which when detected (or in response to a control signal), it will activate the internal power relays and enable the AC output voltage to the terminals coupled to the external load.

Abstract: A high-barrier gate field-effect transistor with an n+-GaAs/p+-GaInP/n-GaAs heterojunctions has been fabricated. The channel contains tri-step doped GaAs layers with a different doping level and thickness in each layer. Due to the significant conduction band discontinuity &Dgr;EC between GaInP/GaAs heterointerface in the gate region, the gate barrier is increased and electrons are effectively confined in the channel. Furthermore, the existence of a valance band discontinuity &Dgr;Ev at the GaInP/GaAs heterointerface may prevent holes generated by impact ionization from reaching the gate region. The tri-step doped channel is adopted to increase the output current and linear transconductance. Therefore the device of this invention provides a high gate-drain breakdown voltage, a low leakage current and a high transconductance. Based on these advantages, the proposed device shows the promise for high-power, large signal analog, and digital switching circuit applications.