Patents by Inventor W. Craig McFadden

W. Craig McFadden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Field effect transistor having control and current electrodes positioned at a planar elevated surface
    Patent number: 5214301
    Abstract: A field effect transistor having regions (20, 20', and 20") which respectively function as a planar elevated surface for gate, drain, and source electrical contact, and method of fabrication. The transistor overlies a substrate (12) and is formed partially from active areas (14 and 14'). The regions (20, 20', and 20"), each underlie or are surrounded by a dielectric layer (22). A gate is formed by a gate layer (24). A source (30) is formed within region (20") and is electrically connected to active area (14'). A drain (30') and channel region are formed within region (20'). Electrical contact is made to the source (30), drain (30') and gate layer (24) by conductive layers (34", 34', and 34, respectively).
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: May 25, 1993
    Assignee: Motorola, Inc.
    Inventors: Yasunobu Kosa, W. Craig McFadden, Keith E. Witek
  • Field effect transistor having control and current electrodes positioned at a planar elevated surface and method of formation
    Patent number: 5158901
    Abstract: A field effect transistor having regions (20, 20', and 20") which respectively function as a planar elevated surface for gate, drain, and source electrical contact, and method of fabrication. The transistor overlies a substrate (12) and is formed partially from active areas (14 and 14'). The regions (20, 20', and 20"), each underlie or are surrounded by a dielectric layer (22). A gate is formed by a gate layer (24). A source (30) is formed within region (20") and is electrically connected to active area (14'). A drain (30') and channel region are formed within region (20'). Electrical contact is made to the source (30), drain (30') and gate layer (24) by conductive layers (34", 34', and 34, respectively).
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: October 27, 1992
    Assignee: Motorola, Inc.
    Inventors: Yasunobu Kosa, W. Craig McFadden, Keith E. Witek