Abstract: A method includes generating a drive signal for a transistor in a switching regulator. The drive signal turns the transistor on and off to generate a regulated output voltage. The drive signal is generated based on a clock signal. The method also includes dynamically decreasing a frequency of the clock signal to decrease a dropout voltage of the switching regulator. Dynamically decreasing the frequency of the clock signal can increase a duration of switching periods defined by the clock signal. The dropout voltage could have a first value proportional to TOFF—MIN/TON—MAX during shorter switching periods and a second value proportional to TOFF—MIN/TON—MAX—DFC during longer switching periods. TOFF—MIN represents a minimum amount of off-time for the transistor during each switching period, TON—MAX represents a maximum amount of on-time for the transistor during shorter switching periods, and TON—MAX—DFC represent a maximum amount of on-time for the transistor during longer switching periods.

Abstract: A switching power supply (96) receives an AC voltage and converts it to a regulated DC voltage. The switching power supply (96) includes a Vcc limiter (16) to limit the operating voltage at the power supply terminal (10) of a integrated regulator circuit (118). The Vcc limiter (16) limits the operating voltage at the power supply terminal (10). When operating voltage at power supply terminal (10) increases, a differential pair of transistors (22, 24) supply a differential current to a current mirror configuration of transistors (26, 30) to supply voltage to a drive transistor (36) to increase current in the drive transistor (36) to a value based on n times the current in a reference transistor (26). An increase in current through the drive transistor (36) counteracts increased operating voltage at the power supply terminal (10), thereby reducing the operating voltage level back to a desired level.

Abstract: A gate driver circuit for switching a MOSFET on and off while reducing the turn off delay of the MOSFET without effecting the turn off slew rate thereof includes a low impedance circuit path between the gate and drain of the MOSFET which is responsive to a control signal for providing discharge of the gate capacitance and a controlled current discharge path for controlling the slew rate of the drain voltage. The low impedance circuit path is automatically disabled once the threshold voltage of the MOSFET is reached and the MOSFET begins to turn off as the drain voltage reaches a predetermined level. As the low impedance circuit path is disabled the controlled current discharge path fixes the slew rate or dv/dt of the drain to source voltage during turn off of the MOSFET.

Abstract: A dual channel switching regulator is disclosed comprising a pair of current mode pulse width modulated controllers synchronized to a single oscillator with the input of the first one of pair of controllers being directly coupled to the oscillator while the input of the second one of the pair of controllers is coupled via an inverter to the output of the oscillator. The pair of controllers are thus operated on alternate half cycles of the output of the oscillator such that the turn off transients of one controller does not affect the other and vice versa. Hence, the switching regulator provides two independent regulated output voltages from an unregulated source.

Abstract: A speakerphone circuit having fast sensitive switching between the receive mode and the transmit mode is disclosed which includes circuitry for providing four point sensing at the input and output of both the transmit and receive attenuators located in the transmit and receive signal paths thereof for controlling the gains of the attenuators in a complementary manner. A logic control circuit comprising a controller circuit provides an attenuator algorithm that first detects that voice signals are present in both signal paths then quickly causes the attenuators to be set to equal gains during a fast idle mode to then allow the stronger of the two signals to set the operating mode of the speakerphone.

Abstract: A DC control loop is disclosed which is used in conjunction with a control circuit to precisely set the maximum control voltage produced by the control circuit for maximizing the gain of an attenuator controlled thereby. The attenuator includes a current mirror having an output for sourcing a DC current the magnitude of which is proportional to the gain of the attenuator and the control circuit includes a capacitor that is charged or discharged accordingly to vary the magnitude of the control voltage. The DC control loop includes a circuit for sinking the current supplied from the current mirror and a current of a predetermined magnitude, the circuit being coupled to the output of the current mirror and a transistor which is turned on when the magnitude of the current from the current mirror equals the magnitude of the current sank by the circuit to inhibit further charge or discharge of the capacitor whereby the gain of the attenuator is held at a predetermined maximum value.

Abstract: A pulse width modulation controller for use in low power current mode switching power supplies includes a unique internal fault timer that initiates restart for overload recovery. The fault timer is responsive to an overload condition for discharging a soft-start capacitor to initiate the restart sequence of the controller.

Abstract: A control circuit for developing a modulated voltage which is proportional to absolute temperature that includes a thermal current source for producing current having a predetermined temperature coefficient and current steering circuitry for proportionally steering the current between first and second outputs in response to a direct current bias voltage applied thereto wherein the current at the first output of the current steering circuitry flows through a resistor. The resistor is connected between a source of different current operating potential and the first output of the current steering circuitry whereby the voltage developed thereacross due to the current steered therethrough is proportional to absolute temperature.

Abstract: An integrated D flip-flop circuit including a plurality of inverter gates produces an output signal having a frequency that is equal to the frequency of an applied alternating input signal divided by a predetermined divide ratio wherein the improvement comprises an additional inverter gate that has an output connected to a predetermined one of the interconnected inverter gates and is responsive to a divide inhibit signal being applied to an input thereof for changing the divide ratio of the D flip-flop circuit.

Abstract: A balanced multiplier circuit for a subscriber loop interface circuit (SLIC) which provides both loop current to a two-wire bidirectional subscriber loop and suppression of longitudinal signals generated at the two-wire loop input to the SLIC while maintaining the midpoint load voltage at half the available power supply voltage applied to the SLIC.

Abstract: A relaxation oscillator which is suited for fabrication as a monolithic circuit and which uses a parallel resistive capacitive frequency determining network wherein a capacitor is charged and discharged between an upper and lower voltage level. As the capacitor is charged to a potential exceeding a first threshold voltage level supplied to a comparator switch, the operating state of the comparator is caused to switch. A current detecting circuit is included which is rendered responsive to a current supplied thereto from a charge circuit when the capacitor is charged substantially to the upper voltage level. The current detecting circuit thereafter actuates a control circuit for switching the threshold voltage applied to the comparator from the first level to a second lower level.

Abstract: A circuit for use with a subscriber loop interface circuit (SLIC) to detect the hook/switch status of the telephone handset driven by the SLIC. Responsive to metallic current flowing through the handset when the telephone is taken off hook, a voltage is derived which exceeds a threshold level as well as a current is produced which is proportional to the value of the metallic current. Whenever the produced current level is less than a predetermined value in conjunction with the threshold level being exceeded, a comparator threshold circuit is rendered operative to produce a signal indicative of the hook status being in a closed switch state. With the hook being in an open switch state, the voltage is caused to be less than the threshold level wherein the comparator threshold circuit is maintained in an non-operative state.

Abstract: A relaxation oscillator which is suited for fabrication as a monolithic circuit and which uses a parallel resistive capacitive frequency determining network wherein a capacitor is charged and discharged between an upper and lower voltage level. As the capacitor is charged to a potential exceeding a first threshold voltage level supplied to a comparator switch, the operating state of the comparator is caused to switch. A current detecting circuit is included which detects a current that is proportional to the charging current supplied to the capacitor from a charge circuit. As the proportional current decreases in value below a predetermined level due to the capacitor being charged to the upper voltage level the current detecting circuit is disabled which actuates a control circuit for switching the threshold voltage applied to the comparator to a lower level.

Abstract: A cancellation circuit which may be utilized in a subscriber loop interface circuit to allow a tone to be supplied in the receive path of the hybrid circuit to be received by the calling subscriber and for cancelling said tone from being transmitted to a called subscriber that is coupled via a carrier channel to the hybrid circuit. The cancellation circuit comprises circuitry responsive to the tone appearing on the transmit path for supplying in-phase and quadrature phase signals at the frequency of this tone to cancel the same to prohibit transmission thereof while simultaneously varying the output impedance of the hybrid circuit at the frequency of the applied tone.

Abstract: A cascode circuit arrangement comprising an input current mirror circuit for providing an output current substantially equal to a supplied input current and an output circuit coupled in cascode to the output of the input current mirror and the output of the circuit. The output circuit comprises a pair of NPN transistors connected in a Darlington amplifier configuration which is supplied a constant bias potential as the input of the amplifier. The Darlington amplifier is coupled in cascode between the output of the current mirror and the output of the current source to buffer the same from variations in the output voltage supplied at the output.

Abstract: In a dual-slope A/D converter employing hysteresis, a reference voltage circuit sets the threshold of the comparator at three distinct levels in response to a ramp control signal and the comparator output. As a reference capacitor ramps through a threshold voltage, the comparator output shifts the threshold with positive feedback (hysteresis) to provide noise immunity. The ramp control signal then shifts the threshold back to its original level cancelling the hysteresis provided at the first comparator trip point. Thus, the comparator switches at the same voltage for both slopes eliminating offset error.

Abstract: This relates to a circuit for delivering a linear voltage (V.sub.P) which is inversely proportional to the capacitance of a pressure sensitive capacitive transducer. A constant current I.sub.O is alternately switched into a reference capacitor (C.sub.R) and the transducer capacitor (C.sub.P). When the voltage across C.sub.P reaches V.sub.P, a flip-flop is toggled to direct current to C.sub.R. When the voltage across C.sub.R reaches a reference voltage (V.sub.R), the flip-flop is again toggled directing current to C.sub.P. A duty cycle detector charges integrator capacitors until the feedback voltage V.sub.P is such as to render equal the charging times of C.sub.P and C.sub.R.

Abstract: The frequency doubler includes circuits for charging and discharging a capacitor at a predetermined rate in response to each incoming cycle. First and second comparators are connected between the capacitor and the input of an OR gate. These comparators limit the magnitudes of the charged voltage and the discharged voltage of the capacitor. The OR gate responds to both comparators being off during a part of the rising portion of the capacitor waveform and during a part of the falling portion of the capacitor waveform by providing pulses having twice the repetition rate as the input pulses. An output circuit may be connected to the output terminal of the OR gate for converting the output signal of the OR gate into a further output signal comprised of current pulses having constant amplitude and duration.

Abstract: A tachometer for measuring and comparing the angular velocity of a first and a second wheel of a vehicle includes means for sensing and generating a train of pulses for each of the wheels wherein the repetition rates of the pulse train varies in proportion to the angular velocity of the wheel. For each of the wheels a frequency doubler is provided for doubling the repetition rate of the pulse train of the varying repetition rates having pulses of the same pulse width and amplitude. For each wheel the frequency doubled pulse train is then integrated to provide a DC output. The two DC outputs for the two wheels are then compared, selected and applied to corresponding output terminals of the tachometer.