Patents by Inventor W. James Scheuermann

W. James Scheuermann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10817184
    Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Cornami, Inc.
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Publication number: 20190155518
    Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Patent number: 10185502
    Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 22, 2019
    Assignee: Cornami, Inc.
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Publication number: 20170262193
    Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Patent number: 9665397
    Abstract: A hardware task manager for an adaptive computing system. The adaptive computing system includes a plurality of computing nodes including an execution unit configured to execute tasks. An interconnection network is operatively coupled to the plurality of computing nodes to provide interconnections among the plurality of computing nodes. The hardware task manager manages execution of the tasks by the execution unit.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: May 30, 2017
    Assignee: Cornami, Inc.
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Publication number: 20150003541
    Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder clement.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 1, 2015
    Inventor: W. James Scheuermann
  • Publication number: 20140331231
    Abstract: A hardware task manager for an adaptive computing system. The adaptive computing system includes a plurality of computing nodes including an execution unit configured to execute tasks. An interconnection network is operatively coupled to the plurality of computing nodes to provide interconnections among the plurality of computing nodes. The hardware task manager manages execution of the tasks by the execution unit.
    Type: Application
    Filed: July 15, 2014
    Publication date: November 6, 2014
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Patent number: 8782196
    Abstract: A hardware task manager for an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from tasks. Likewise, output buffers must also be available before the task can start to execute and store results. The hardware task manager maintains a counter associated with each buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and the buffer is not ready and the associated task cannot run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared indicating the input buffer has sufficient data and is available to be processed.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 15, 2014
    Assignee: Sviral, Inc.
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Patent number: 8767804
    Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: July 1, 2014
    Assignee: QST Holdings LLC
    Inventor: W. James Scheuermann
  • Publication number: 20130117404
    Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.
    Type: Application
    Filed: June 11, 2012
    Publication date: May 9, 2013
    Applicant: Sviral, Inc.
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Publication number: 20130044792
    Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 21, 2013
    Inventor: W. James Scheuermann
  • Patent number: 8249135
    Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder clement.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: August 21, 2012
    Assignee: QST Holdings LLC
    Inventor: W. James Scheuermann
  • Patent number: 8200799
    Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: June 12, 2012
    Assignee: QST Holdings LLC
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Patent number: 8130825
    Abstract: A video processor uses attributes of video data to perform encoding and decoding. Some embodiments dynamically configure the processor via a sequence of instructions, where the instructions include information on the attributes of the current video data. Some embodiments include a dynamically configurable adder array that computes difference functions thereby generating error vectors. Some embodiments include a dynamically configurable adder array that computes filtering functions applied to the video data, e.g. interpolation or decimation of the incoming video prior to motion detection. Some embodiments of the invention provide dynamically configurable hardware searches, for example, for detecting motion. Some embodiments of the invention are implemented using an adaptive computing machines (ACMs). An ACM includes a plurality of heterogeneous computational elements, each coupled to an interconnection network.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: March 6, 2012
    Assignee: NVIDIA Corporation
    Inventor: W. James Scheuermann
  • Patent number: 8126949
    Abstract: A reconfigurable filter node including an input data memory adapted to store a plurality of input data values, a filter coefficient memory adapted to store a plurality of filter coefficient values, and a plurality of computational units adapted to simultaneously compute filter data values. Filter data values are the outputs of a filter in response to input data values or a second plurality of filter coefficients to be used in subsequent filter data value computations. First and second input data registers load successive input data values input data memory or from adjacent computational units. Each computational unit comprises a pre-adder adapted to output either the sum two input data values stored in the computational unit or alternately to output a single input data value, and a multiply-and-accumulate unit adapted to multiply the output of the pre-adder by a filter coefficient and accumulate the result.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: February 28, 2012
    Assignee: NVIDIA Corporation
    Inventors: W. James Scheuermann, Otis Lamont Frost, III
  • Patent number: 8018463
    Abstract: A video processor according to the invention is dynamically configurable as to the attributes of the video data upon which the processor operates. Some embodiments dynamically configure the processor via a sequence of instructions, where the instructions include information on the attributes of the current video data. Some embodiments include a dynamically configurable adder array that computes difference functions thereby generating error vectors. Some embodiments include a dynamically configurable adder array that computes filtering functions applied to the video data, e.g. interpolation or decimation of the incoming video prior to motion detection. Some embodiments of the invention provide dynamically configurable hardware searches, for example, for detecting motion. Some embodiments of the invention are implemented using an adaptive computing machines (ACMs). An ACM includes a plurality of heterogeneous computational elements, each coupled to an interconnection network.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: September 13, 2011
    Assignee: NVIDIA Corporation
    Inventor: W. James Scheuermann
  • Publication number: 20110002409
    Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder clement.
    Type: Application
    Filed: August 20, 2010
    Publication date: January 6, 2011
    Applicant: QST HOLDINGS, LLC
    Inventor: W. James Scheuermann
  • Patent number: 7822109
    Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: October 26, 2010
    Assignee: QST Holdings, LLC.
    Inventor: W. James Scheuermann
  • Patent number: 7809050
    Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: October 5, 2010
    Assignee: QST Holdings, LLC
    Inventor: W. James Scheuermann
  • Publication number: 20100037029
    Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.
    Type: Application
    Filed: February 9, 2009
    Publication date: February 11, 2010
    Applicant: QST HOLDINGS LLC
    Inventors: W. James SCHEUERMANN, Eugene B. HOGENAUER