Patents by Inventor W. James Scheuermann
W. James Scheuermann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10817184Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.Type: GrantFiled: January 22, 2019Date of Patent: October 27, 2020Assignee: Cornami, Inc.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Publication number: 20190155518Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.Type: ApplicationFiled: January 22, 2019Publication date: May 23, 2019Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 10185502Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.Type: GrantFiled: May 25, 2017Date of Patent: January 22, 2019Assignee: Cornami, Inc.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Publication number: 20170262193Abstract: A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.Type: ApplicationFiled: May 25, 2017Publication date: September 14, 2017Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 9665397Abstract: A hardware task manager for an adaptive computing system. The adaptive computing system includes a plurality of computing nodes including an execution unit configured to execute tasks. An interconnection network is operatively coupled to the plurality of computing nodes to provide interconnections among the plurality of computing nodes. The hardware task manager manages execution of the tasks by the execution unit.Type: GrantFiled: July 15, 2014Date of Patent: May 30, 2017Assignee: Cornami, Inc.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Publication number: 20150003541Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder clement.Type: ApplicationFiled: July 1, 2014Publication date: January 1, 2015Inventor: W. James Scheuermann
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Publication number: 20140331231Abstract: A hardware task manager for an adaptive computing system. The adaptive computing system includes a plurality of computing nodes including an execution unit configured to execute tasks. An interconnection network is operatively coupled to the plurality of computing nodes to provide interconnections among the plurality of computing nodes. The hardware task manager manages execution of the tasks by the execution unit.Type: ApplicationFiled: July 15, 2014Publication date: November 6, 2014Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 8782196Abstract: A hardware task manager for an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from tasks. Likewise, output buffers must also be available before the task can start to execute and store results. The hardware task manager maintains a counter associated with each buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and the buffer is not ready and the associated task cannot run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared indicating the input buffer has sufficient data and is available to be processed.Type: GrantFiled: June 11, 2012Date of Patent: July 15, 2014Assignee: Sviral, Inc.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 8767804Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.Type: GrantFiled: August 20, 2012Date of Patent: July 1, 2014Assignee: QST Holdings LLCInventor: W. James Scheuermann
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Publication number: 20130117404Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.Type: ApplicationFiled: June 11, 2012Publication date: May 9, 2013Applicant: Sviral, Inc.Inventors: W. James Scheuermann, Eugene B. Hogenauer
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Publication number: 20130044792Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.Type: ApplicationFiled: August 20, 2012Publication date: February 21, 2013Inventor: W. James Scheuermann
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Patent number: 8249135Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder clement.Type: GrantFiled: August 20, 2010Date of Patent: August 21, 2012Assignee: QST Holdings LLCInventor: W. James Scheuermann
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Patent number: 8200799Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.Type: GrantFiled: February 9, 2009Date of Patent: June 12, 2012Assignee: QST Holdings LLCInventors: W. James Scheuermann, Eugene B. Hogenauer
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Patent number: 8130825Abstract: A video processor uses attributes of video data to perform encoding and decoding. Some embodiments dynamically configure the processor via a sequence of instructions, where the instructions include information on the attributes of the current video data. Some embodiments include a dynamically configurable adder array that computes difference functions thereby generating error vectors. Some embodiments include a dynamically configurable adder array that computes filtering functions applied to the video data, e.g. interpolation or decimation of the incoming video prior to motion detection. Some embodiments of the invention provide dynamically configurable hardware searches, for example, for detecting motion. Some embodiments of the invention are implemented using an adaptive computing machines (ACMs). An ACM includes a plurality of heterogeneous computational elements, each coupled to an interconnection network.Type: GrantFiled: May 9, 2005Date of Patent: March 6, 2012Assignee: NVIDIA CorporationInventor: W. James Scheuermann
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Patent number: 8126949Abstract: A reconfigurable filter node including an input data memory adapted to store a plurality of input data values, a filter coefficient memory adapted to store a plurality of filter coefficient values, and a plurality of computational units adapted to simultaneously compute filter data values. Filter data values are the outputs of a filter in response to input data values or a second plurality of filter coefficients to be used in subsequent filter data value computations. First and second input data registers load successive input data values input data memory or from adjacent computational units. Each computational unit comprises a pre-adder adapted to output either the sum two input data values stored in the computational unit or alternately to output a single input data value, and a multiply-and-accumulate unit adapted to multiply the output of the pre-adder by a filter coefficient and accumulate the result.Type: GrantFiled: December 7, 2007Date of Patent: February 28, 2012Assignee: NVIDIA CorporationInventors: W. James Scheuermann, Otis Lamont Frost, III
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Patent number: 8018463Abstract: A video processor according to the invention is dynamically configurable as to the attributes of the video data upon which the processor operates. Some embodiments dynamically configure the processor via a sequence of instructions, where the instructions include information on the attributes of the current video data. Some embodiments include a dynamically configurable adder array that computes difference functions thereby generating error vectors. Some embodiments include a dynamically configurable adder array that computes filtering functions applied to the video data, e.g. interpolation or decimation of the incoming video prior to motion detection. Some embodiments of the invention provide dynamically configurable hardware searches, for example, for detecting motion. Some embodiments of the invention are implemented using an adaptive computing machines (ACMs). An ACM includes a plurality of heterogeneous computational elements, each coupled to an interconnection network.Type: GrantFiled: May 9, 2005Date of Patent: September 13, 2011Assignee: NVIDIA CorporationInventor: W. James Scheuermann
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Publication number: 20110002409Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder clement.Type: ApplicationFiled: August 20, 2010Publication date: January 6, 2011Applicant: QST HOLDINGS, LLCInventor: W. James Scheuermann
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Patent number: 7822109Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.Type: GrantFiled: March 28, 2003Date of Patent: October 26, 2010Assignee: QST Holdings, LLC.Inventor: W. James Scheuermann
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Patent number: 7809050Abstract: Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.Type: GrantFiled: October 13, 2009Date of Patent: October 5, 2010Assignee: QST Holdings, LLCInventor: W. James Scheuermann
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Publication number: 20100037029Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.Type: ApplicationFiled: February 9, 2009Publication date: February 11, 2010Applicant: QST HOLDINGS LLCInventors: W. James SCHEUERMANN, Eugene B. HOGENAUER