Abstract: A method of forming a reinforced composite structure comprises providing a plurality of fiberglass rovings to a resin applicator. The plastic applicator has an inlet, an outlet, and a plastic applicator cavity such that the rovings enter the plastic applicator through the inlet and exit through the outlet. The inlet and outlet are relatively positioned to spread out the rovings. Resin-containing rovings are directed between a first fiberglass matt and a second fiberglass matt and then cured. A joint that connects two frame members formed by the method of the invention is provided.

Abstract: A method of forming a reinforced composite structure comprises providing a plurality of fiberglass rovings to a resin applicator. The plastic applicator has an inlet, an outlet, and a plastic applicator cavity such that the rovings enter the plastic applicator through the inlet and exit through the outlet. The inlet and outlet are relatively positioned to spread out the rovings. Resin-containing rovings are directed between a first fiberglass matt and a second fiberglass matt and then cured. A joint that connects two frame members formed by the method of the invention is provided.

Abstract: A method of measuring blood flow through a blood vessel is provided using a single quasi-continuous mode probe that can support multiple frequencies without increasing the probe tip size. A plurality of elements are provided in the probe tip. Each element emits ultrasound waves using a long pulsed signal with each element having a different resonant frequency. Each element also receives ultrasound energy in a continuous mode. A selector is manually controlled by a practitioner to select the active element. The output may take a variety of forms. For example, the output may be printed, displayed, recorded to a memory, and/or played through a speaker or headset.

Abstract: According to one embodiment, the present invention relates to a method and a system for efficient transaction processing.

Abstract: A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal and image processing. One or more such circuits are provided on an integrated circuit. A video or image frame generation system is constructed from one or more of these integrated circuits, optionally with additional memory circuitry, to provide exceptional performance in frame production for animation, particularly 3-D and other high performance applications such as medical imaging, virtual reality and real-time scene generation in video games and simulation environments. The circuit(s) are used to process high speed object-oriented graphics related streams such as proposed by MPEG 4, as well as act as a single chip JAVA engine with highly optimized numeric performance.

Abstract: A system for equalizing the voltages across first and second batteries coupled in series at a common terminal comprising a capacitive storage element, first and second inductive storage elements, first and second switch circuits, and a control unit. The capacitive storage element is coupled to first and second nodes. The first inductive storage element is coupled between the first node and the first battery. The second inductive storage element is coupled between the second node and the second battery. The first switch circuit is coupled between the first node and the common terminal. The second switch circuit is coupled between the second node and the common terminal. The control circuit operates the first and second switch circuits to control current flow to the first and second batteries.

Abstract: An arithmetic circuit for calculating floating point operations. The circuit comprises first and second blocks of consecutive logic cells. Each logic block has a first cell and a last cell, with the first cell through the next to last cell having an output that is coupled to the next adjacent cell. The coupling of the last cells of the first and second logic blocks depends on the value of a control signal. A comparator may be used to generate the control signal.

Abstract: A bearing system and journal which may incorporate either a sleeve or a ball bearing. The system includes a bearing journal having a sleeve bearing portion and a ball bearing portion. When a sleeve bearing is used in the system, a first end of the sleeve bearing is supported in the sleeve bearing portion of the journal, and a second end of the sleeve bearing is supported by a finger spring. The sleeve bearing and finger spring are retained within the journal by an end cap, which is press-fit into the ball bearing portion of the journal. When a ball bearing is used in the system, the ball bearing may be press-fit directly into the ball bearing portion of the bearing journal, or press-fit into a spacer, which is press-fit into the ball bearing portion of the bearing journal.

Abstract: A multi-port packet processor on an integrated circuit provides an efficient means to interface multiple high-speed packet-based communications channels. The multi-port packet processor includes multiple port processors. Each port processor can include a channel interface for coupling to a respective communications channel, a channel processor for processing the data packets received through the channel interface, and an interprocessor communications interface for providing communication between the port processors. The channel interface can be designed to process data packets using a particular set of packet-based protocols. Alternatively, the channel interface can be designed having programmable controls to allow processing of data packets using a selected set, from a number of possible sets, of packet-based protocols.

Abstract: A digital electronic circuit for performing single precision floating point arithmetic involving multiple operations of multiplication, and addition or subtraction. Multiple operations may occur within each time unit of operation.

Abstract: A multi-port packet processor on an integrated circuit provides an efficient means to interface multiple high-speed packet-based communications channels. The multi-port packet processor includes multiple port processors. Each port processor can include a channel interface for coupling to a respective communications channel, a channel processor for processing the data packets received through the channel interface, and an interprocessor communications interface for providing communication between the port processors. The channel interface can be designed to process data packets using a particular set of packet-based protocols. Alternatively, the channel interface can be designed having programmable controls to allow processing of data packets using a selected set, from a number of possible sets, of packet-based protocols.

Abstract: A device for performing single precision floating point arithmetic. The device includes a shared operand generator that receives an operand and outputs a result that is a fixed function of the operand. It also includes an arithmetic circuit comprising a plurality of multiply circuits that calculate partial products of a first and second operand and the result of the shared operand generator. It also includes circuitry to calculate the sum of the partial products and a third operand to produce the arithmetic result.

Abstract: A bearing system and journal which may incorporate either a sleeve or a ball bearing. The system includes a bearing journal having a sleeve bearing portion and a ball bearing portion. When a sleeve bearing is used in the system, a first end of the sleeve bearing is supported in the sleeve bearing portion of the journal, and a second end of the sleeve bearing is supported by a finger spring. The sleeve bearing and finger spring are retained within the journal by an end cap, which is press-fit into the ball bearing portion of the journal. When a ball bearing is used in the system, the ball bearing may be press-fit directly into the ball bearing portion of the bearing journal, or press-fit into a spacer, which is press-fit into the ball bearing portion of the bearing journal.

Abstract: A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal and image processing. One or more such circuits are provided on an integrated circuit. A video or image frame generation system is constructed from one or more of these integrated circuits, optionally with additional memory circuitry, to provide exceptional performance in frame production for animation, particularly 3-D and other high performance applications such as medical imaging, virtual reality and real-time scene generation in video games and simulation environments. The circuit(s) are used to process high speed object-oriented graphics related streams such as proposed by MPEG 4, as well as act as a single chip JAVA engine with highly optimized numeric performance.

Abstract: A digital certificate includes framing characters defining a protected area. The protected area contains a selected set of components, including text-based components and binary-based components, and the certificate serves as a transport container for such components. A message digest or hashing algorithm applied to the protected area provides consistent results despite modifications to the certificate outside the protected area. A digital signature provides authentication of source and content integrity. Digital certificates under the present invention may be applied to a variety of purposes including but not limited to proof of ownership, gift certificates, upgrade purchases, and other applications where verification of source and content integrity are desirable.

Abstract: Computer systems may be provided with additional performance for demanding applications while adding little additional hardware. For example, a slave device for a host computer system combines an embedded programmable controller with non-volatile memory, local RAM, and interface logic. The host computer system treats the slave device as if it would be a hierarchical memory system such as a conventional disk drive on which it may store and retrieve files. Additionally, the host computer system may program the controller to perform operations on stored information, including image processing and/or data compression. The non-volatile memory may include a disk drive, writable CD-ROM, optical drive, or non-volatile solid state memory.

Abstract: Digital product dissemination and sale occurs across a broad spectrum of distribution platforms making available a packaged digital product for wide spread public distribution. Execution of a packaged digital product on a purchasing consumer's personal computer provides opportunity to the user-consumer for purchase and delivery of the digital product. The user-consumer triggers a purchase step conducted automatically and directly between the personal computer and a bank network. A publishing merchant need not be involved in the purchase step other than receiving credit for the purchase in the credit card bank network. Delivery of the digital product following purchase occurs automatically and without use of cumbersome encryption keys.

Abstract: A system and method for allowing telephone-based interactive performance of financial transactions in multiple languages. The system prompts the customer of a financial institution in various languages until the customer's language and home country are identified. The system then connects the customer telephonically with a representative who speaks the customer's language and who can authorize the transaction by accessing the customer's records. Authorization by the local representative and record keeping are also provided.

Abstract: A programmable logic device (PLD) and configurable logic network in which one or more logic combination networks (LCN) each receives logic inputs from two or more PLDs (PLD1, PLD2) and generates logic outputs (O, P) which provide inputs to programmable selectors (POR, UCL, . . . ) for controlling implementation of logic functions of various types and functionality by a controllable logic function sub-network by routing through the sub-network, logic values and logic instructions originating externally of the PLD's. Each programmable logic device includes an AND logic array (FAND . . . ) having inputs for receiving signals (Ax, Bx) and generating product term output signals and an OR logic array (OG . . . ) having inputs for receiving signals and generating sum term output signals (OF . . . ).

Abstract: A fetal monitor is provided for gathering characteristic data such as fetal electrocardiogram, temperature and intra-uterine pressure so that fetal health may be determined during intra-operative and postoperative periods. The fetal monitor comprises a remote sensing unit, the remote sensing unit containing sensors which continually sample fetal temperature and electrocardiogram. A transceiver is housed in the remote sensing unit and outputs the sampled fetal temperature and electrocardiogram signals to an external antenna. A monitoring station is provided for monitoring the fetal temperature and electrocardiogram signals from the antenna. Additionally, a pressure transducer may be housed in the remote sensing unit for continually sampling intra-uterine pressure. This intra-uterine pressure signal in combination with the above signals are utilized to determine fetal health or the onset and progress of parturition.