Abstract: A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.

Abstract: A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.

Abstract: A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation.

Abstract: During execution of a code sequence, a profile is generated containing addresses of the data cache misses experienced during the execution. The profile is associated with the code sequence such that, during a future execution of the code sequence, the profile is available. Prefetching may be performed, based on the profile. Since the profile records a sequence of miss addresses, an arbitrarily complex miss pattern can be prefetched. In one embodiment, multiple profiles may be associated with a code sequence having multiple entry points (e.g. multiple instructions at which execution may begin within the code sequence). When the code sequence is executed, the profile associated with the entry point of the current execution may be selected. Additionally, a new profile may be generated. If the entry point of the current execution is not associated with a profile, the new profile is saved.

Abstract: A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation.

Abstract: During execution of a code sequence, a profile is generated containing addresses of the data cache misses experienced during the execution. The profile is associated with the code sequence such that, during a future execution of the code sequence, the profile is available. Prefetching may be performed, based on the profile. Since the profile records a sequence of miss addresses, an arbitrarily complex miss pattern can be prefetched. In one embodiment, multiple profiles may be associated with a code sequence having multiple entry points (e.g. multiple instructions at which execution may begin within the code sequence). When the code sequence is executed, the profile associated with the entry point of the current execution may be selected. Additionally, a new profile may be generated. If the entry point of the current execution is not associated with a profile, the new profile is saved.

Abstract: A computer system supports a touch command which may be used to open a page in the main memory. Microprocessors within the computer system may determine an appropriate time at which to perform the touch command, and then transmit the touch command to the memory controller within the computer system. In response to the touch command, the memory controller opens the selected page but may not return data from the page. Subsequent memory operations may experience a page hit memory latency instead of a page miss memory latency due to the occurrence of the touch command. Data bus bandwidth is not consumed by the touch command. The touch command may be used even if actually prefetching data is not desirable. The microprocessors in the computer system may monitor which pages are experiencing cache hits within the microprocessors. If a page is experiencing cache hits, a cache miss within the page may be more probable. The touch command may be used to prepare the main memory system for a potential cache miss.

Abstract: A branch prediction unit includes a cache-line based branch prediction storage having a branch prediction storage location assigned to each cache line of an instruction cache within the microprocessor employing the branch prediction unit. Although each branch prediction storage location is assigned to a particular cache line, the branch prediction storage location stores an alternate target indication indicating whether a branch prediction within the storage location corresponds to a branch instruction within the cache line to which the storage location is assigned or to a branch instruction within a different cache line. The different cache line has a predetermined relationship to the cache line to which the storage location is assigned. In various embodiments, the different cache line is at an index one less than the index of the storage location or is within a different way of the same index.