Abstract: A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the processor elements is selectively coupled to a corresponding bit position of the memory row of data, performing the same computational operation on a selected plurality of data bits in parallel, and writing the result into the memory at the same row as the data was read from.

Abstract: A communication structure and method which allows connection-like and connectionless communications to be provided on a multiplexed link is provided. The structure and method can make efficient use of available transmission capacity and/or network resources while providing for both types of communication. Connection-like communications can be provided by a channel having allocated bandwidth dedicated to the communication while connectionless communication can be provided by a shared channel through which data can be transmitted to subscribers. In an embodiment, the shared channel transmits frames of packets addressed to one or more of the subscribers. The frames can have a robustly packaged header that can be received by all subscriber stations serviced by the base station while payload data in the frame can be packaged with a level of robustness appropriate for the intended subscriber station. Different packagings can include different encoding and/or modulation of the payload data.

Abstract: A communication structure and method which allows connection-like and connectionless communications to be provided on a multiplexed link is provided. The structure and method can make efficient use of available transmission capacity and/or network resources while providing both types of communication and hybrids. Connection-like communications can be provided by a channel having allocated transmission capacity dedicated to the communication while connectionless communication can be provided by a shared channel through which data can be transmitted to subscribers. In an embodiment, the shared channel transmits frames of packets addressed to one or more of the subscribers. The allocation of transmission capacity between the dedicated channels and the shared channel can be fixed, or can be managed to meet network or network operator requirements. The structure and method can also be managed by the network operator to permit prioritization of some communications over others.

Abstract: A financial transaction system operable to manage purchases of at least one of goods and services, comprising a customer identifier that is operable to uniquely identify an account to which the purchases are being charged; a financial services provider operable to at least one of debit and credit the account to which the purchases are being charged; a plurality of point-of-sale (POS) terminals in communication with the financial services provider via an intermediary node, where the point of sale terminals are operable to gather purchase information, customer identification and authorization information, and display information provided from a financial services provider; and a plurality of software agents distributed within the financial transaction system, operable to negotiate rules and behaviors for the purchase of goods and services.

Abstract: A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the processor elements is selectively coupled to a corresponding bit position of the memory row of data, performing the same computational operation on a selected plurality of data bits in parallel, and writing the result into the memory at the same row as the data was read from.

Abstract: A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the processor elements is selectively coupled to a corresponding bit position of the memory row of data, performing the same computational operation on a selected plurality of data bits in parallel, and writing the result into the memory at the same row from which the data was read.

Abstract: An apparatus is presented which, carried by or embedded in a lonely or socially inept individual, communicates with like devices in such a way as to divine the likelihood of attraction due to relative sexual, social, intellectual or spiritual interests of the bearers. It may either be programmed explicitly by a trusted body, or suspect compatibility by observing and mining patterns of behaviour, environment and physiological response in the users of the said devices. The users are signalled or led to initial interaction in such a way as to maximize the likelihood of prolonged and deepened contact.

Abstract: An interprocessor communication system is used in a multiprocessor where each processor is simultaneously a transmitter and a receiver of data. A data bus having only two states, a default state and an active state (e.g. high and low levels), is coupled to a plurality of bi-directional bus transceivers. Each transceiver is coupled between a processor element and a data bus and has an enable input. When the transceiver is enabled, it propagates an active level received at one end, either the processor element end or the data bus end, to the other end. The active state dominates on the interprocessor bus, so for instance, when multiple processors transmit, if any processor transmits a low level, then the bus will be low and all processors with enabled transceivers will also receive that low signal. This can be used for broadcasting data or combine operations such as AND or minimum.

Abstract: A digital computer performs read-modify-write (RMW) processing on each bit of a row of memory in parallel, in one operation cycle, comprising: (a) addressing a memory, (b) reading each bit of a row of data from the memory in parallel, (c) performing the same computational operation on each bit of the data in parallel, using an arithmetic logic unit (ALU) in a dedicated processing element, and (d) writing the result of the operation back into the original memory location for each bit in the row.

Abstract: A random access memory chip comprising static random access storage elements, word lines and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines, a separate processor element connected to each of the sense amplifiers, apparatus for addressing a word line, and apparatus for applying a single instruction to the processor elements, whereby the instructed processor elements are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the addressed word line. A method of operating a digital computer comprising in one operation cycle, addressing a memory, reading each of a row of data from the memory in parallel, and performing an operation function on each bit of the data in parallel to provide a result.

Abstract: A random access memory chip is comprised of static random access storage elements, word lines, and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines, a separate processor element connected to each of the sense amplifiers, apparatus for addressing a word line, and apparatus for applying a single instruction to the processor elements, whereby the instructed processor elements are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the addressed word line. A method of operating a digital computer is comprised of in one operation cycle, addressing a memory, reading each of a row of data from the memory in parallel, and performing a same operation function on each bit of the data in parallel to provide a result.