Abstract: A data scrambler-descrambler combination is illustrated which stores previously modified received data and alters data passing through on the basis of certain of the previously stored data bits. Additionally, the previously stored data is monitored to detect repetitive patterns, which indicate that the scrambler is no longer properly scrambling the signal, and introducing a pattern breaking data bit into the storage means whenever such a pattern is detected.

Abstract: A multiple data path simulator for use with a data generator having a clock output and a data output including a data delay with a predetermined number of outputs, a data multiplexer for selecting one of the outputs, a clock delay with a predetermined number of outputs corresponding to those of the data delay, a clock multiplexer for selecting one of the clock delay outputs and a gray code counter for determining which outputs are selected is disclosed. Multiplexers determine which outputs are main and which are standby. A second clock multiplexer is one time delay behind the first clock multiplexer and provides clock to the gray code counter when counting up. The gray code counter uses the output of the first clock multiplexer when counting down.

Abstract: A system is disclosed for transferring words from an input source to a computer bus which can issue an acknowledge or a negative acknowledge signal. The system includes registers for storing the words to be transferred. It further includes control circuitry for initiating the transfer of a first word on the output bus, and, if negatively acknowledged, retrying the transfer. The control circuitry is further capable of initiating, before the retry, the transfer on the bus of another word or words received from the input source after the first word.

Abstract: A data processing system is disclosed in which memory modules are connected at ports of interconnecting buses, with the physical addresses of the modules not necessarily being contiguous. The system includes a random access memory for translating contiguous logical memory addresses, as generated by a processor, to the physical addresses of the memory modules. The operation of the random access memory is such that memory modules of various sizes can be used together. Switching is provided for selectively interchanging word address bits and module address bits before the transformation is performed by the random access memory, thereby providing interleaving.

Abstract: A circuit card is disclosed of the type for connection to a system by means of connector pins on the card. The circuit card includes a soft power switch for reducing the power transient effects of inserting the card by gradually coupling the circuit load on the card to the system power supply voltage. Connector pins of various extensions are used to initiate events in the coupling of the circuit load to the power supply voltage. The card further includes logic which causes the circuit load to be gradually decoupled from the power supply upon removal of the card from the system.