Patents by Inventor W. Riyon Harding

W. Riyon Harding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7536496
    Abstract: A method and apparatus for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: W. Riyon Harding, David W. Milton, Clarence Rosser Ogilvie, Jason E. Rotella, Paul M. Schanely, Sebastian T. Ventrone
  • Publication number: 20080276034
    Abstract: A design structure, which may be generated by a fabless design company, for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.
    Type: Application
    Filed: July 25, 2008
    Publication date: November 6, 2008
    Inventors: W. Riyon Harding, David W. Milton, Clarence Rosser Ogilvie, Jason E. Rotella, Paul M. Schanely, Sebastian T. Ventrone
  • Patent number: 7085913
    Abstract: A method and structure for an integrated circuit is disclosed. The invention includes a plurality of logic cores, a plurality of local hubs connected to said logic cores, and a plurality of global hubs connected to said local hubs. The local hubs and the global hubs transfer data between the logic cores.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: W. Riyon Harding, Sebastian T. Ventrone
  • Patent number: 6944698
    Abstract: A method and apparatus for providing bus arbitrations in a multiprocessor system is disclosed. A computer system includes a common bus that is shared by multiple cores, such as processors. A history of bus requests for the common bus made by the cores is stored in a bus request history table. In response to bus request made by the cores, the common bus is arbitrated according to information stored in the bus request history table by an arbiter.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: September 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: W. Riyon Harding, Thomas Michael Lepsic, Sebastian Theodore Ventrone
  • Publication number: 20040006660
    Abstract: A method and apparatus for providing bus arbitrations in a multiprocessor system is disclosed. A computer system includes a common bus that is shared by multiple cores, such as processors. A history of bus requests for the common bus made by the cores is stored in a bus request history table. In response to bus request made by the cores, the common bus is arbitrated according to information stored in the bus request history table by an arbiter.
    Type: Application
    Filed: July 8, 2002
    Publication date: January 8, 2004
    Applicant: International Business Machines Corporation
    Inventors: W. Riyon Harding, Thomas Michael Lepsic, Sebastian Theodore Ventrone
  • Publication number: 20030154324
    Abstract: A method and structure for an integrated circuit is disclosed. The invention includes a plurality of logic cores, a plurality of local hubs connected to said logic cores, and a plurality of global hubs connected to said local hubs. The local hubs and the global hubs transfer data between the logic cores.
    Type: Application
    Filed: February 13, 2002
    Publication date: August 14, 2003
    Applicant: International Business Machines Corporation
    Inventors: W. Riyon Harding, Sebastian Ventrone