Abstract: A method is provided for determining specifications that meet electronic system or integrated circuit product requirements at all stages of the product lifecycle. Early in the product lifecycle design features must be specified. Later in the lifecycle datasheet specifications must be determined and published to customers, and test specifications in manufacturing must be determined. The method includes acquiring data from a test vehicle, fitting the data to a copula-based statistical model using an appropriately programmed computer, and using the statistical model to compute producer- and customer-oriented figures of merit of a product, different from the test vehicle, using the appropriately programmed computer. Different size, fault tolerance schemes, test coverage, end-use (datasheet), and test condition specifications of the product may be modeled. The statistical model is a copula-based and so can take into account dependency among attributes of the product.

Abstract: A method is provided for determining specifications that meet electronic system or integrated circuit product requirements at all stages of the product lifecycle. Early in the product lifecycle design features must be specified. Later in the lifecycle datasheet specifications must be determined and published to customers, and test specifications in manufacturing must be determined. The method includes acquiring data from a test vehicle, fitting the data to a copula-based statistical model using an appropriately programmed computer, and using the statistical model to compute producer- and customer-oriented figures of merit of a product, different from the test vehicle, using the appropriately programmed computer. Different size, fault tolerance schemes, test coverage, end-use (datasheet), and test condition specifications of the product may be modeled. The statistical model is a copula-based and so can take into account dependency among attributes of the product.

Abstract: An active inductor circuit implemented in sub-micron CMOS semiconductor technology is usable at gigaHertz frequencies and includes an input node, a non-inverting transconductor circuit comprising a differential pair of NMOS transistors connected to the input node, an inverting transconductor circuit comprising an NMOS transistor connected to an output node of the non-inverting transconductor circuit and connected to the input node in a gyrator feedback configuration. Varactors coupled to the transconductor circuits tune the frequency and Q of the active inductor circuit.

Abstract: A method for testing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.

Abstract: A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the graded integrated circuits.