Abstract: An arbitration mechanism is distributed among channel units of a statistically multiplexed frame relay switching system serving a plurality of access lines, the cumulative bandwidth of which exceeds that of an aggregate data link over which data is to be transported. For each access line, an arbitration code is generated. This code includes a transmit request or start bit, a calculated multibit arbitration value based upon a combination of parameters, including queuing delay and the configuration and traffic rate of the line, and an address code that identifies the physical location of the respective channel unit. All arbitration codes are readable by each frame relay channel unit via a wire-ORed bus. A channel unit participating in an arbitration cycle compares the value of its arbitration code with those of the other participants.

Abstract: A multi-circuit emulating line card is installable in a single line card slot of the backplane of digital switch, and is configured to emulate the functionality of each of a plurality of digital switch line cards, respectively associated with plural digital subscriber circuits served by the switch. In the course of emulating these plural line cards, the multi-circuit line card provides connectivity between each digital subscriber circuit and a digital carrier communication link to plural digital subscriber loop circuits, such as BRITE cards of a remote terminal site. The line card of the invention also includes network and subscriber circuit-associated metallic link impedance simulation circuits for terminating a metallic test bus.

Abstract: A multi-circuit emulating line card is installable in a single line card slot of the backplane of digital switch, and is configured to emulate the functionality of each of a plurality of digital switch line cards, respectively associated with plural digital subscriber circuits served by the switch. In the course of emulating these plural line cards, the multi-circuit line card provides connectivity between each digital subscriber circuit and a digital carrier communication link to plural digital subscriber loop circuits, such as BRITE cards of a remote terminal site. The line card of the invention also includes network and subscriber circuit-associated metallic link impedance simulation circuits for terminating a metallic test bus.

Abstract: In order to transport digital data across a reliable digital communication link from a transmit site to a destination site, the data is processed in parallel paths to derive error detection information, such as a cyclic redundancy code, and to encode the data. The outputs of the parallel paths are combined into a composite digital data sequence, which is then transmitted over the reliable digital communication link to the destination site. At the destination site, the encoded digital data component of the composite data sequence is decoded and then subjected to the same error detection operation carried out at the transmit site to derive error detection information associated with the decoded digital data. This recalculated error detection information is compared with the error detection information component contained in the composite digital data sequence. If there is a mismatch, the reliable digital communication link and the encoder at the transmit site and the decoder at the destination site are reset.

Abstract: State of the art data compression-protocol engines provide high compression ratios for improving data transport over a high data rate serial communication link. However, a respective data port of data terminal equipment may not be capable of being clocked at a sufficiently high clock rate, which limits the performance of the data compression-protocol engine, and prevents full utilization of the available bandwidth of the serial link. To remedy this problem, data terminal equipment and data compression-protocol engine components that provide auxiliary data communication port connectivity are employed. Data from the data terminal equipment is clocked to the data compression-protocol engine over a plurality of parallel data paths. This increases the effective clock rate and enables the data compression-protocol engine to output a compressed data stream that fully utilizes the bandwidth of the network.

Abstract: Network bit efficiency for transmitting a limited size data frame over a digital communication system is enhanced by a macro-header encoding mechanism which replaces plural header portions of a data frame sequence with a single macro-header byte. The macro-header may be representative of protocol and signal processing operation fields that would otherwise require a longer overhead sequence as a precursor to data transmission. At the receiver, the macro-code is translated into a predefined sequence of opcodes, parameters and data bytes. Whenever the receiver requires another opcode, parameter or data byte, it initially looks to the macro-code. Otherwise, the necessary byte is obtained from the data frame segment being interpreted.

Abstract: In a time division multiplexed digital communication network through which time division multiplexed data signals are routed over respectively different transmission paths of the network, the paths having respectively different transmission delays, to a bonding receiver at a destination end of the network, the bonding receiver including a digital signal processor for controlling the operation of the bonding receiver, bonding compensation that is normally carried out entirely by the digital signal processor is transferred from the digital signal processor to an auxiliary delay path, which is coupled to the receive path from the network. The auxiliary delay path is controlled by the direct memory access (DMA) functionality of the digital signal processor to transfer selected data time slots through the auxiliary delay path.