Patents by Inventor W. T. Greer, Jr.

W. T. Greer, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Writable logic array
    Patent number: 4796229
    Abstract: A writable logic array includes a first matrix (12,38) of gate elements. Program lines (16) connect the first array (12,38) with a second matrix (18,40) of gate elements. A plurality of switches (22), one for each program line (16), selectively couple or decouple the program lines (16) to the second matrix (18,40). Switches (22) are in turn controlled by a volatile memory (32), into which instructions may be written at the time the system into which the array is incorporated is booted up.
    Type: Grant
    Filed: July 8, 1986
    Date of Patent: January 3, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: W. T. Greer, Jr., Frank L. Laczko
  • Read back latch
    Patent number: 4758739
    Abstract: A read-back latch circuit which includes a latch circuit having an input and an output and an enable input and operative to transmit an input data signal to the output in response to a preselected enable signal and to block the transmission of the input data signal otherwise. A read-back switch is coupled between the output and input of said latch circuit and is operative to couple the signal on the output of said latch circuit to the input thereof in response to a read-back control signal.
    Type: Grant
    Filed: September 24, 1986
    Date of Patent: July 19, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Kevin M. Ovens, W. T. Greer, Jr.