Abstract: A system for detecting fraudulent activity using account analytics obtains an interaction record for an interaction between a remote device and a user account via an interaction channel, where the interaction is an attempt to access the user account, obtains historical data relating to the user account and the interaction channel that includes one or more historical interaction records relating to the user account and activity records relating to the interaction channel, calculates a threat score for the user account based on the interaction record and the one or more historical interaction records that indicates a likelihood that the user account is subject to fraudulent activity, generates a database record based on the interaction record that includes the threat score, and initiates corrective action if the threat score exceeds a predetermined threshold.

Abstract: An architecture for assessing and identifying fraudulent contact with client contact systems, such as IVR, includes threshold and machine learning scoring and filtering of calls based on these criteria. The criteria may include behavioral, situational and reputational scoring.

Abstract: An architecture for assessing and identifying fraudulent contact with client contact systems, such as IVR, includes threshold and machine learning scoring and filtering of calls based on these criteria. The criteria may include behavioral, situational and reputational scoring.

Abstract: An architecture for assessing and identifying fraudulent contact with client contact systems, such as IVR, includes threshold and machine learning scoring and filtering of calls based on these criteria. The criteria may include behavioral, situational and reputational scoring.

Abstract: An architecture for assessing and identifying fraudulent contact with client contact systems, such as IVR, includes threshold and machine learning scoring and filtering of calls based on these criteria. The criteria may include behavioral, situational and reputational scoring.

Abstract: An architecture for assessing and identifying fraudulent contact with client contact systems, such as IVR, includes threshold and machine learning scoring and filtering of calls based on these criteria. The criteria may include behavioral, situational and reputational scoring.

Abstract: A data processing system comprising an accelerator that acts as a common shared resource for plural applications executing in respective virtual machines. The data processing system includes an interface mapping unit that facilitates the submission of tasks from applications to the accelerator. The interface mapping unit includes physical registers that act as physical register input/output interfaces for the accelerator. The interface mapping unit exposes a plurality of virtual accelerator input/output interfaces to the applications that are then dynamically mapped to the physical register input/output interfaces by the interface mapping unit to allow applications to access, and thereby submit a task to, a given physical register input/output interface.

Abstract: A data processing system 20 comprising an accelerator 12 that acts as a common shared resource for plural applications 3 executing in respective virtual machines 4, 5. The data processing system 20 includes an interface mapping unit 21 that facilitates the submission of tasks from applications to the accelerator 12. The interface mapping unit 21 includes physical registers 8 that act as physical register input/output interfaces for the accelerator 12. The interface mapping unit 21 exposes a plurality of virtual accelerator input/output interfaces 22 to the applications 3 that are then dynamically mapped to the physical register input/output interfaces 8 by the interface mapping unit 21 to allow applications to access, and thereby submit a task to, a given physical register input/output interface 8.

Abstract: Methods for responding to a potential incident are provided in which data about the potential incident is received from a first remote sensing unit. Additional remote sensing units are identified that may have additional data about the potential incident, and additional data about the potential incident is received from at least some of these additional remote sensing units. The totality of the received data is then analyzed, and at least one remote entity is automatically notified regarding the occurrence of the potential incident.

Abstract: Methods for responding to a potential incident are provided in which data about the potential incident is received from a first remote sensing unit. Additional remote sensing units are identified that may have additional data about the potential incident, and additional data about the potential incident is received from at least some of these additional remote sensing units. The totality of the received data is then analyzed, and at least one remote entity is automatically notified regarding the occurrence of the potential incident.

Abstract: Methods for responding to a potential incident are provided in which data about the potential incident is received from a first remote sensing unit. Additional remote sensing units are identified that may have additional data about the potential incident, and additional data about the potential incident is received from at least some of these additional remote sensing units. The totality of the received data is then analyzed, and at least one remote entity is automatically notified regarding the occurrence of the potential incident.

Abstract: Methods for responding to a potential incident are provided in which data about the potential incident is received from a first remote sensing unit. Additional remote sensing units are identified that may have additional data about the potential incident, and additional data about the potential incident is received from at least some of these additional remote sensing units. The totality of the received data is then analyzed, and at least one remote entity is automatically notified regarding the occurrence of the potential incident.

Abstract: A dependency table stores a reorder buffer tag for each register. The stored reorder buffer tag corresponds to the last of the instructions within the reorder buffer (in program order) to update the register. Otherwise, the dependency table indicates that the value stored in the register is valid. When operand fetch is performed for a set of concurrently decoded instructions, dependency checking is performed including checking for dependencies between the set of concurrently decoded instructions as well as accessing the dependency table to select the reorder buffer tag stored therein. Either the reorder buffer tag of one of the concurrently decoded instructions, the reorder buffer tag stored in the dependency table, the instruction result corresponding to the stored reorder buffer tag, or the value from the register itself is forwarded as the source operand for the instruction. Information from the comparators and the information stored in the dependency table is sufficient to select which value is forwarded.

Abstract: A dependency table stores a reorder buffer tag for each register. When operand fetch is performed for a set of concurrently decoded instructions, dependency checking is performed including checking for dependencies between the set of concurrently decoded instructions as well as accessing the dependency table to select the reorder buffer tag stored therein. Either the reorder buffer tag of one of the concurrently decoded instructions, the reorder buffer tag stored in the dependency table, the instruction result corresponding to the stored reorder buffer tag, or the value from the register itself is forwarded as the source operand for the instruction. The dependency table stores the width of the register being updated. Prior to forwarding the reorder buffer tag stored within the dependency table, the width stored therein is compared to the width of the source operand being requested.

Abstract: A superscalar microprocessor includes a reorder buffer to correctly handle dependency checking and multiple updates to the same destination. The reorder buffer stores instructions in program order, and retires instructions that have executed and the results obtained. When a instruction is retired, the results of the instruction are stored and the memory space in the reorder buffer is deallocated. The results of the retired instructions are stored to a register file via a retire bus. If the results of two or more retired instructions output to the same register in the register file, then only the newest instruction, the later instruction in the original program sequence, is stored to the program register. The register file has a plurality of write ports for the transfer of data via the retire bus. If two retired instructions output to the same register, then a write port is not utilized. The retire window is the number of instructions monitored for retirement.

Abstract: A dependency table stores a reorder buffer tag for each register. The stored reorder buffer tag corresponds to the last of the instructions within the reorder buffer (in program order) to update the register. Otherwise, the dependency table indicates that the value stored in the register is valid. When operand fetch is performed for a set of concurrently decoded instructions, dependency checking is performed including checking for dependencies between the set of concurrently decoded instructions as well as accessing the dependency table to select the reorder buffer tag stored therein. Either the reorder buffer tag of one of the concurrently decoded instructions, the reorder buffer tag stored in the dependency table, the instruction result corresponding to the stored reorder buffer tag, or the value from the register itself is forwarded as the source operand for the instruction. Information from the comparators and the information stored in the dependency table is sufficient to select which value is forwarded.

Abstract: A register rename unit employs a rename map stack upon which a register rename map corresponding to each dispatched instruction is pushed. Upon occurrence of an exception, the register rename maps corresponding to instructions subsequent to the instruction experiencing the exception are popped from the stack. In this manner, the architected register to implemented register mapping consistent with the instruction experiencing the exception is restored. According to one embodiment, the rename map stack can be recovered from an exception in one clock cycle. In one particular implementation, the rename map stack comprises multiple independent stacks. Each independent stack corresponds to one of the architected registers, and stores implemented register specifiers corresponding to that architected register.

Abstract: A register rename unit employs a rename map stack upon which a register rename map corresponding to each dispatched instruction is pushed. Upon occurrence of an exception, the register rename maps corresponding to instructions subsequent to the instruction experiencing the exception are popped from the stack. In this manner, the architected register to implemented register mapping consistent with the instruction experiencing the exception is restored. According to one embodiment, the rename map stack can be recovered from an exception in one clock cycle. In one particular implementation, the rename map stack comprises multiple independent stacks. Each independent stack corresponds to one of the architected registers, and stores implemented register specifiers corresponding to that architected register.

Abstract: A reorder buffer is provided which decouples allocation of storage space within the buffer for storing instructions from forwarding of the corresponding operands. When instructions are presented to the reorder buffer for storage and dependency checking, the reorder buffer allocates storage for the instructions and corresponding instruction results. If an unresolved dependency is detected, the instructions remain stored in the reorder buffer but operand forwarding is delayed until the unresolved dependency becomes resolved. Advantageously, the previously included extra storage and multiplexing prior to dependency checking may be eliminated. Additional clock cycle time may be available for performing dependency checking. Additionally, area formerly occupied by the extra storage is freed for other purposes.

Abstract: A superscalar microprocessor includes a reorder buffer to correctly handle dependency checking and multiple updates to the same destination. The reorder buffer stores instructions in program order, and retires instructions that have executed and the results obtained. When a instruction is retired, the results of the instruction are stored and the memory space in the reorder buffer is deallocated. The results of the retired instructions are stored to a register file via a retire bus. If the results of two or more retired instructions output to the same register in the register file, then only the newest instruction, the later instruction in the original program sequence, is stored to the program register. The register file has a plurality of write ports for the transfer of data via the retire bus. If two retired instructions output to the same register, then a write port is not utilized. The retire window is the number of instructions monitored for retirement.