Patents by Inventor Wade A. Walker
Wade A. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6249862Abstract: A dependency table stores a reorder buffer tag for each register. The stored reorder buffer tag corresponds to the last of the instructions within the reorder buffer (in program order) to update the register. Otherwise, the dependency table indicates that the value stored in the register is valid. When operand fetch is performed for a set of concurrently decoded instructions, dependency checking is performed including checking for dependencies between the set of concurrently decoded instructions as well as accessing the dependency table to select the reorder buffer tag stored therein. Either the reorder buffer tag of one of the concurrently decoded instructions, the reorder buffer tag stored in the dependency table, the instruction result corresponding to the stored reorder buffer tag, or the value from the register itself is forwarded as the source operand for the instruction. Information from the comparators and the information stored in the dependency table is sufficient to select which value is forwarded.Type: GrantFiled: November 15, 2000Date of Patent: June 19, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Muralidharan S. Chinnakonda, Thang M. Tran, Wade A. Walker
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Patent number: 6209084Abstract: A dependency table stores a reorder buffer tag for each register. When operand fetch is performed for a set of concurrently decoded instructions, dependency checking is performed including checking for dependencies between the set of concurrently decoded instructions as well as accessing the dependency table to select the reorder buffer tag stored therein. Either the reorder buffer tag of one of the concurrently decoded instructions, the reorder buffer tag stored in the dependency table, the instruction result corresponding to the stored reorder buffer tag, or the value from the register itself is forwarded as the source operand for the instruction. The dependency table stores the width of the register being updated. Prior to forwarding the reorder buffer tag stored within the dependency table, the width stored therein is compared to the width of the source operand being requested.Type: GrantFiled: May 5, 2000Date of Patent: March 27, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Muralidharan S. Chinnakonda, Thang M. Tran, Wade A. Walker
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Patent number: 6189089Abstract: A superscalar microprocessor includes a reorder buffer to correctly handle dependency checking and multiple updates to the same destination. The reorder buffer stores instructions in program order, and retires instructions that have executed and the results obtained. When a instruction is retired, the results of the instruction are stored and the memory space in the reorder buffer is deallocated. The results of the retired instructions are stored to a register file via a retire bus. If the results of two or more retired instructions output to the same register in the register file, then only the newest instruction, the later instruction in the original program sequence, is stored to the program register. The register file has a plurality of write ports for the transfer of data via the retire bus. If two retired instructions output to the same register, then a write port is not utilized. The retire window is the number of instructions monitored for retirement.Type: GrantFiled: January 6, 1999Date of Patent: February 13, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Wade A. Walker, D. T. Matheny
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Patent number: 6108769Abstract: A dependency table stores a reorder buffer tag for each register. The stored reorder buffer tag corresponds to the last of the instructions within the reorder buffer (in program order) to update the register. Otherwise, the dependency table indicates that the value stored in the register is valid. When operand fetch is performed for a set of concurrently decoded instructions, dependency checking is performed including checking for dependencies between the set of concurrently decoded instructions as well as accessing the dependency table to select the reorder buffer tag stored therein. Either the reorder buffer tag of one of the concurrently decoded instructions, the reorder buffer tag stored in the dependency table, the instruction result corresponding to the stored reorder buffer tag, or the value from the register itself is forwarded as the source operand for the instruction. Information from the comparators and the information stored in the dependency table is sufficient to select which value is forwarded.Type: GrantFiled: May 17, 1996Date of Patent: August 22, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Muralidharan S. Chinnakonda, Thang M. Tran, Wade A. Walker
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Patent number: 5987596Abstract: A register rename unit employs a rename map stack upon which a register rename map corresponding to each dispatched instruction is pushed. Upon occurrence of an exception, the register rename maps corresponding to instructions subsequent to the instruction experiencing the exception are popped from the stack. In this manner, the architected register to implemented register mapping consistent with the instruction experiencing the exception is restored. According to one embodiment, the rename map stack can be recovered from an exception in one clock cycle. In one particular implementation, the rename map stack comprises multiple independent stacks. Each independent stack corresponds to one of the architected registers, and stores implemented register specifiers corresponding to that architected register.Type: GrantFiled: May 12, 1999Date of Patent: November 16, 1999Assignee: Advanced Micro Devices, Inc.Inventor: Wade A. Walker
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Patent number: 5944812Abstract: A register rename unit employs a rename map stack upon which a register rename map corresponding to each dispatched instruction is pushed. Upon occurrence of an exception, the register rename maps corresponding to instructions subsequent to the instruction experiencing the exception are popped from the stack. In this manner, the architected register to implemented register mapping consistent with the instruction experiencing the exception is restored. According to one embodiment, the rename map stack can be recovered from an exception in one clock cycle. In one particular implementation, the rename map stack comprises multiple independent stacks. Each independent stack corresponds to one of the architected registers, and stores implemented register specifiers corresponding to that architected register.Type: GrantFiled: December 10, 1998Date of Patent: August 31, 1999Assignee: Advanced Micro Devices, Inc.Inventor: Wade A. Walker
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Patent number: 5922069Abstract: A reorder buffer is provided which decouples allocation of storage space within the buffer for storing instructions from forwarding of the corresponding operands. When instructions are presented to the reorder buffer for storage and dependency checking, the reorder buffer allocates storage for the instructions and corresponding instruction results. If an unresolved dependency is detected, the instructions remain stored in the reorder buffer but operand forwarding is delayed until the unresolved dependency becomes resolved. Advantageously, the previously included extra storage and multiplexing prior to dependency checking may be eliminated. Additional clock cycle time may be available for performing dependency checking. Additionally, area formerly occupied by the extra storage is freed for other purposes.Type: GrantFiled: October 27, 1998Date of Patent: July 13, 1999Assignee: Advanced Micro Devices, Inc.Inventor: Wade A. Walker
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Patent number: 5903740Abstract: A superscalar microprocessor includes a reorder buffer to correctly handle dependency checking and multiple updates to the same destination. The reorder buffer stores instructions in program order, and retires instructions that have executed and the results obtained. When a instruction is retired, the results of the instruction are stored and the memory space in the reorder buffer is deallocated. The results of the retired instructions are stored to a register file via a retire bus. If the results of two or more retired instructions output to the same register in the register file, then only the newest instruction, the later instruction in the original program sequence, is stored to the program register. The register file has a plurality of write ports for the transfer of data via the retire bus. If two retired instructions output to the same register, then a write port is not utilized. The retire window is the number of instructions monitored for retirement.Type: GrantFiled: July 24, 1996Date of Patent: May 11, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Wade A. Walker, David T. Matheny
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Patent number: 5881305Abstract: A register rename unit employs a rename map stack upon which a register rename map corresponding to each dispatched instruction is pushed. Upon occurrence of an exception, the register rename maps corresponding to instructions subsequent to the instruction experiencing the exception are popped from the stack. In this manner, the architected register to implemented register mapping consistent with the instruction experiencing the exception is restored. According to one embodiment, the rename map stack can be recovered from an exception in one clock cycle. In one particular implementation, the rename map stack comprises multiple independent stacks. Each independent stack corresponds to one of the architected registers, and stores implemented register specifiers corresponding to that architected register.Type: GrantFiled: December 13, 1996Date of Patent: March 9, 1999Assignee: Advanced Micro Devices, Inc.Inventor: Wade A. Walker
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Patent number: 5870580Abstract: A reorder buffer is provided which decouples allocation of storage space within the buffer for storing instructions from forwarding of the corresponding operands. When instructions are presented to the reorder buffer for storage and dependency checking, the reorder buffer allocates storage for the instructions and corresponding instruction results. If an unresolved dependency is detected, the instructions remain stored in the reorder buffer but operand forwarding is delayed until the unresolved dependency becomes resolved. Advantageously, the previously included extra storage and multiplexing prior to dependency checking may be eliminated. Additional clock cycle time may be available for performing dependency checking. Additionally, area formerly occupied by the extra storage is freed for other purposes.Type: GrantFiled: December 13, 1996Date of Patent: February 9, 1999Assignee: Advanced Micro Devices, Inc.Inventor: Wade A. Walker
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Patent number: 5765016Abstract: A reorder buffer including a speculative storage section and a retired storage section is provided. The speculative storage section stores speculative register states; while the retired storage section stores committed register states corresponding to the execution of instructions which have been retired. The dependency checking logic of the reorder buffer checks dependencies for operands of instructions being dispatched against both the speculative and retired storage sections. In this manner, a dependency is always detected within the reorder buffer. Therefore, no selection between a register file value and a value provided from the reorder buffer need be made. In fact, the register file may be eliminated from a microprocessor employing the reorder buffer. The retired storage section comprises a shiftable queue in one embodiment. The shiftable queue stores committed register states and indications of the architected registers corresponding to the committed register states.Type: GrantFiled: September 12, 1996Date of Patent: June 9, 1998Assignee: Advanced Micro Devices, Inc.Inventor: Wade A. Walker
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Patent number: 5363582Abstract: This invention provides a hook setting device which uses levers to provide the desired force multiplication factor and force pattern to a fishing line where the force is supplied by one or a combination of tension or compression force means. A trigger means and cautilevered weight of the apparatus provides an initial force or resistance to set the hook in the fish and the levers and force means maintain a preselected force pattern and intensity on the fishing cord.Type: GrantFiled: April 27, 1988Date of Patent: November 15, 1994Inventors: Wade A. Walker, Danny C. Reaves
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Patent number: D1060740Type: GrantFiled: February 17, 2023Date of Patent: February 4, 2025Assignee: Marine Equipment Company, LLCInventors: Wade A Walker, Donald F Baker, Preston J Cobb