Abstract: An electrostatic discharge (ESD) protection circuit includes a field oxide device in a substrate, wherein the field oxide device is coupled between an input/output (I/O) pad and a first terminal. The field oxide device includes a drain end and a source end having a first type of dopant. The field oxide device includes a field oxide structure between the drain end and the source end. The field oxide structure has a top surface co-planar with a top surface of a substrate. A first doped region having a second type of dopant is adjacent to the drain end. A second doped region having the second type of dopant is adjacent to the source end. The field oxide structure is in a well and the source end and the drain end are separate from the well. The substrate has the second type of dopant and is around the field oxide structure.

Abstract: An electrostatic discharge (ESD) protection circuit includes a field oxide device in a substrate, wherein the field oxide device is coupled between an input/output (I/O) pad and a first terminal. The field oxide device includes a drain end and a source end having a first type of dopant. The field oxide device includes a field oxide structure between the drain end and the source end. The field oxide structure has a top surface co-planar with a top surface of a substrate. A first doped region having a second type of dopant is adjacent to the drain end. A second doped region having the second type of dopant is adjacent to the source end. The field oxide structure is in a well and the source end and the drain end are separate from the well. The substrate has the second type of dopant and is around the field oxide structure.

Abstract: An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad is provided. The ESD protection circuit includes a first field oxide device coupled between a first terminal that is capable of providing a first supply voltage and the I/O pad. The first field oxide device includes a drain end having a first type of dopant and a source end having the first type of dopant. The first field oxide device includes a first doped region having a second type of dopant disposed adjacent to the drain end of the first field oxide device and a second doped region having the second type of dopant disposed adjacent to the source end of the first field oxide device.

Abstract: An electrostatic discharge (ESD) protection circuit includes a clamp transistor, and inverter, a resistance-capacitance (RC) circuit, and a current mirror. The clamp transistor is coupled between a first supply node and a second supply node. The inverter has an input end and an output end, and the output end of the inverter is coupled with a gate of the clamp transistor. The RC circuit is coupled to the first supply node. The current mirror includes a first transistor and a second transistor. The first transistor is coupled between the input end of the inverter and the second supply node, and the second transistor is coupled between the RC circuit and the second supply node.

Abstract: An electrostatic discharge (ESD) protection circuit includes a clamp transistor, and inverter, a resistance-capacitance (RC) circuit, and a current mirror. The clamp transistor is coupled between a first supply node and a second supply node. The inverter has an input end and an output end, and the output end of the inverter is coupled with a gate of the clamp transistor. The RC circuit is coupled to the first supply node. The current mirror includes a first transistor and a second transistor. The first transistor is coupled between the input end of the inverter and the second supply node, and the second transistor is coupled between the RC circuit and the second supply node.

Abstract: An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current mirror is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.

Abstract: An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad is provided. The ESD protection circuit includes a first field oxide device coupled between a first terminal that is capable of providing a first supply voltage and the I/O pad. The first field oxide device includes a drain end having a first type of dopant and a source end having the first type of dopant. The first field oxide device includes a first doped region having a second type of dopant disposed adjacent to the drain end of the first field oxide device and a second doped region having the second type of dopant disposed adjacent to the source end of the first field oxide device.

Abstract: An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current minor is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.