Patents by Inventor Wadie N. Khadder

Wadie N. Khadder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5200347
    Abstract: A method is provided for use with an integrated circuit which includes a npn bipolar transistor on which a variable thickness oxide layer has been formed, the method for improving the radiation hardness of the transistor comprising the steps of: removing the variable thickness oxide layer; and forming a new oxide layer on the transistor, the new oxide layer having less overall volume than the removed variable thickness oxide layer.
    Type: Grant
    Filed: February 14, 1991
    Date of Patent: April 6, 1993
    Assignee: Linear Technology Corporation
    Inventors: Jia-Tarng Wang, Robert T. Haraga, Wadie N. Khadder
  • Patent number: 5012305
    Abstract: A high speed BIFET junction field effect transistor is formed in an epitaxial layer of one conductivity type and includes source and drain regions of opposite conductivity type interconnected by a thin channel region of the opposite conductivity type. A thin surface layer of the one conductivity type is formed over the channel region, and a highly conductive contact is formed on the surface layer intermediate the source and drain regions. The surface contact can comprise highly doped polycrystalline silicon material with a metal layer on the surface thereof. The surface contact and the epitaxial layer underlying the channel region comprise gates for the field effect transistor. Increased speed of operation comes from the increased conductivity of the surface contact.
    Type: Grant
    Filed: July 13, 1990
    Date of Patent: April 30, 1991
    Assignee: Linear Technology Corporation
    Inventors: Wadie N. Khadder, James P. Vokac, Robert C. Dobkin
  • Patent number: 4588454
    Abstract: A process for doping a semiconductor material is performed during a deposition phase in a plurality of steps, first at a relatively low temperature to form a high concentration glass formation layer of the dopant on a semiconductor wafer at a high rate, and then raising the temperature slowly to provide an initial drive-in of the dopant. After etch removal of excess glass formation, the wafers are subjected to a base diffusion at an elevated temperature in an oxidizing atmosphere.
    Type: Grant
    Filed: December 21, 1984
    Date of Patent: May 13, 1986
    Assignee: Linear Technology Corporation
    Inventors: Wadie N. Khadder, Jia-Tarng Wang
  • Patent number: 4512816
    Abstract: A semiconductor substrate having an epitaxial layer on its upper surface is provided with a masking layer. Holes are photolithographically etched in the masking layer where isolation diffusion regions are to be formed. Then aluminum ions are implanted into the surface and diffused completely through the epitaxial layer so as to create tubs of epitaxial material that are PN junction isolated. Since aluminum is a fast diffuser, the diffusion time is greatly reduced, thereby reducing the up diffusion of buried N+ collector so that the original epitaxial layer can be made relatively thin. Lateral isolation diffusion is reduced, thereby substantially reducing the surface area required for isolation. Thus, the process is capable of increasing the component density in the completed integrated circuit.
    Type: Grant
    Filed: April 23, 1984
    Date of Patent: April 23, 1985
    Assignee: National Semiconductor Corporation
    Inventors: Amolak R. Ramde, Wadie N. Khadder, Surinder Krishna
  • Patent number: 4512815
    Abstract: In a monolithic semiconductor integrated circuit, conventional bipolar transistors are fabricated along with thin ion implanted junction field effect transistors, to create BIFET structures. After the conventional isolation diffusion, the surface oxide is stripped off and the semiconductor wafer ion implanted with slow diffusing impurities of a conductivity type, the same as the undiffused surface material. Then the bipolar transistors, along with the junction field effect transistors, are fabricated using conventional oxide masked diffusion processes. The field effect device sources and drains employ the base diffusions of the bipolar transistors while the gate contact is achieved with an emitter diffusion. The field effect device channels are formed at a depth substantially greater than that of the impurities deposited in the original ion implant. If desired, an ion implanted top gate can be established over the channel. The wafer is then annealed and processed in accordance with conventional techniques.
    Type: Grant
    Filed: January 31, 1983
    Date of Patent: April 23, 1985
    Assignee: National Semiconductor Corporation
    Inventors: Wadie N. Khadder, Jia T. Wang, Brian E. Hollins
  • Patent number: 4412238
    Abstract: In a monolithic semiconductor integrated circuit, conventional bipolar transistors are fabricated along with thin ion implanted junction field effect transistors, to create BIFET structures. After the conventional isolation diffusion, the surface oxide is stripped off and the semiconductor wafer ion implanted with slow diffusing impurities of a conductivity type, the same as the undiffused surface material. Then the bipolar transistors, along with the junction field effect transistors, are fabricated using conventional oxide masked diffusion processes. The field effect device sources and drains employ the base diffusions of the bipolar transistors while the gate contact is achieved with an emitter diffusion. The field effect device channels are formed at a depth substantially greater than that of the impurities deposited in the original ion implant. If desired, an ion implanted top gate can be established over the channel. The wafer is then annealed and processed in accordance with conventional techniques.
    Type: Grant
    Filed: May 27, 1980
    Date of Patent: October 25, 1983
    Assignee: National Semiconductor Corporation
    Inventors: Wadie N. Khadder, Jia T. Wang, Brian E. Hollins
  • Patent number: 4373253
    Abstract: A process for fabricating JFET devices into a conventional CMOS monolithic IC. The combination of devices provides linear circuit operation with low noise characteristics.
    Type: Grant
    Filed: April 13, 1981
    Date of Patent: February 15, 1983
    Assignee: National Semiconductor Corporation
    Inventors: Wadie N. Khadder, Jia-Tarng Wang, James E. Solomon
  • Patent number: RE34821
    Abstract: A high speed BIFET junction field effect transistor is formed in an epitaxial layer of one conductivity type and includes source and drain regions of opposite conductivity type interconnected by a thin channel region of the opposite conductivity type. A thin surface layer of the one conductivity type is formed over the channel region, and a highly conductive contact is formed on the surface layer intermediate the source and drain regions. The surface contact can comprise highly doped polycrystalline silicon material with a metal layer on the surface thereof. The surface contact and the epitaxial layer underlying the channel region comprise gates for the field effect transistor. Increased speed of operation comes from the increased conductivity of the surface contact.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: January 3, 1995
    Assignee: Linear Technology Corporation
    Inventors: Wadie N. Khadder, James P. Vokac, Robert C. Dobkin