Patents by Inventor Wah Lim
Wah Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136478Abstract: Lighting systems and methods of combining visible and non-visible light converting phosphor are presented herein. A method comprises varying respective amounts of a non-visible light converting phosphor and respective amounts of a visible light converting phosphor that are included in respective encapsulants that have been used to encapsulate LED chips of respective samples of a group of LED chips within respective LED test packages; based on determined mathematical relationships and correlations associated with the varying, including a first amount of the non-visible light converting phosphor and a second amount of the visible light converting phosphor in an encapsulant; and encapsulating, using the encapsulant, a manufacturing portion of the group of LED chips within respective LED packages to facilitate categorization of the respective LED packages into a manufacturing bin represented by a defined target LED package light output intensity and a defined target LED package light output color coordinate.Type: ApplicationFiled: January 4, 2024Publication date: April 25, 2024Inventors: TEK BENG LOW, ENG WAH TAN, CHEE SHENG LIM
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Publication number: 20240136279Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Applicant: Intel CorporationInventors: Min Suet Lim, Telesphor Kamgaing, Chee Kheong Yoon, Chu Aun Lim, Eng Huat Goh, Jooi Wah Wong, Kavitha Nagarajan
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Publication number: 20240136243Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Applicant: Intel CorporationInventors: Min Suet Lim, Telesphor Kamgaing, Ilan Ronen, Kavitha Nagarajan, Chee Kheong Yoon, Chu Aun Lim, Eng Huat Goh, Jooi Wah Wong
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Publication number: 20240126228Abstract: Systems or methods of the present disclosure may provide for implementing design software that is used to design a configuration for a programmable fabric of a programmable logic device. Implementing the design software includes receiving, at a processor, design configuration details for the configuration. Implementing the design software also includes receiving, at the processor, a plurality of constraints including a thermal constraint for the configuration. Moreover, implementing the design software comprises performing thermal aware resource selection based at least in part on the thermal constraint. Furthermore, implementing the design software includes causing the programmable logic device to be operated to stay within the thermal constraint.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Inventors: Archanna Srinivasan, Teik Wah Lim, Pravin Chander Chandran
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Publication number: 20240113700Abstract: Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.Type: ApplicationFiled: December 8, 2023Publication date: April 4, 2024Inventors: Christopher P. MOZAK, Ralph S. LI, Chin Wah LIM, Mahmoud ELASSAL, Anant BALAKRISHNAN, Isaac ALI
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Patent number: 11916554Abstract: Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.Type: GrantFiled: December 16, 2019Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Christopher P. Mozak, Ralph S. Li, Chin Wah Lim, Mahmoud Elassal, Anant Balakrishnan, Isaac Ali
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Publication number: 20240027279Abstract: A method is provided for thermally monitoring an integrated circuit during operation of the integrated circuit. The method includes receiving a measurement of a temperature in a circuit design for the integrated circuit from a temperature sensor, and determining a hottest temperature in the circuit design based on the measurement of the temperature. A non-transitory computer readable storage medium includes computer readable instructions stored thereon for causing a computing system to receive a measurement of a first temperature in a circuit design for an integrated circuit from a temperature sensor, and determine a second temperature of a cold spot in an active region of the circuit design by adjusting the measurement of the first temperature generated by the temperature sensor by an offset.Type: ApplicationFiled: September 28, 2023Publication date: January 25, 2024Applicant: Intel CorporationInventors: Krishnakumar Varadarajan, Aurelien Mozipo, Juan Cevallos Palomeque, Teik Wah Lim, Aanandh Balasubramanian
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Publication number: 20230037609Abstract: Examples described herein relate to an interface and a network interface device coupled to the interface and comprising circuitry to: control power utilization by a first set of one or more devices based on power available to a system that includes the first set of one or more devices, wherein the system is communicatively coupled to the network interface and control cooling applied to the first set of one or more devices.Type: ApplicationFiled: September 28, 2022Publication date: February 9, 2023Inventors: Paniraj GURURAJA, Navneeth JAYARAJ, Mahammad Yaseen Isasaheb MULLA, Nitesh GUPTA, Hemanth MADDHULA, Laxminarayan KAMATH, Jyotsna BIJAPUR, Delraj Gambhira DAMBEKANA, Vikrant THIGLE, Amruta MISRA, Anand HARIDASS, Rajesh POORNACHANDRAN, Krishnakumar VARADARAJAN, Sudipto PATRA, Nikhil RANE, Teik Wah LIM
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Patent number: 11411555Abstract: Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.Type: GrantFiled: August 5, 2021Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Ee Wah Lim, Lay Leng Lim
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Publication number: 20220215147Abstract: An integrated circuit system includes a temperature sensor circuit that generates an output indicative of a temperature in an integrated circuit. The integrated circuit system also includes a temperature management controller circuit that compares the temperature indicated by the output of the temperature sensor circuit to a temperature threshold. The integrated circuit system further includes temperature reduction circuitry and/or design compilation techniques and partial or full reconfiguration that controls the temperature in the integrated circuit system. The temperature management controller circuit causes the temperature reduction circuitry to reduce the temperature in response to the temperature indicated by the output of the temperature sensor circuit exceeding the temperature threshold. The temperature sensor circuit, the temperature management controller circuit, and the temperature reduction circuitry may be implemented by soft logic circuits, hard logic circuits, or any combination thereof.Type: ApplicationFiled: March 24, 2022Publication date: July 7, 2022Applicant: Intel CorporationInventors: Teik Wah Lim, Rajiv Mongia, Archanna Srinivasan, Mahesh A. Iyer
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Publication number: 20210367588Abstract: Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.Type: ApplicationFiled: August 5, 2021Publication date: November 25, 2021Inventors: Ee Wah Lim, Lay Leng Lim
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Patent number: 11088682Abstract: Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.Type: GrantFiled: December 14, 2018Date of Patent: August 10, 2021Assignee: Intel CorporationInventors: Ee Wah Lim, Lay Leng Lim
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Publication number: 20200195240Abstract: Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.Type: ApplicationFiled: December 14, 2018Publication date: June 18, 2020Applicant: Intel CorporationInventors: Ee Wah Lim, Lay Leng Lim
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Publication number: 20200119721Abstract: Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Christopher P. MOZAK, Ralph S. LI, Chin Wah LIM, Mahmoud ELASSAL, Anant BALAKRISHNAN, Isaac ALI
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Patent number: 10530367Abstract: The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.Type: GrantFiled: December 28, 2018Date of Patent: January 7, 2020Assignee: Intel CorporationInventors: Chooi Pei Lim, Teik Wah Lim, Boon Haw Ooi, Keong Hong Oh
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Publication number: 20190140647Abstract: The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Chooi Pei Lim, Teik Wah Lim, Boon Haw Ooi, Keong Hong Oh
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Patent number: 10164517Abstract: A voltage regulator package includes a voltage regulator module that outputs a voltage signal of a particular voltage level through an output terminal is provided. The voltage regulator module may be switched on according to a periodic signal having a periodic signal frequency as a variable. The periodic signal frequency may be tuned to reduce impedance, jitter, or noise.Type: GrantFiled: August 17, 2016Date of Patent: December 25, 2018Assignee: ALTERA CORPORATIONInventors: Teik Wah Lim, Ashraf Lotfi
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Patent number: 10103627Abstract: A packaged integrated circuit and method of forming the same. The package integrated circuit includes an integrated circuit formed on a semiconductor die affixed to a surface of a multi-layer substrate, and a switch-mode regulator formed on the semiconductor die (or another semiconductor die) affixed to the surface of the multi-layer substrate. The integrated circuit and the switch-mode regulator are integrated within a package to form the packaged integrated circuit.Type: GrantFiled: February 26, 2015Date of Patent: October 16, 2018Assignee: Altera CorporationInventors: Teik Wah Lim, Ashraf W. Lotfi, Choong Kit Wong, John Weld
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Publication number: 20180257815Abstract: A casted corner and bottom for a multi-purpose carrier having top, bottom, and vertical rails includes (a) a casted corner with a top face and at least three hollow faces with openings for mounting with the top and vertical rails from three directions; (b) a padeye arranged diagonally on the top face, the padeye provided with an aperture allowing the multi-purpose carrier to be craned or lifted; and (c) a casted bottom with at least three openings for mounting with the bottom and vertical rails or a transport case. The bottom face of the casted bottom is hollow with a diagonally arranged slot. The casted corner and casted bottom are mounted respectively onto the top and bottom corners of the multi-purpose carrier and/or transport case, which are securely liftable and stackable with the padeye of the casted corner inserted into the slot of the casted bottom.Type: ApplicationFiled: December 4, 2015Publication date: September 13, 2018Inventor: Poh Wah LIM
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Publication number: 20180054110Abstract: A voltage regulator package includes a voltage regulator module that outputs a voltage signal of a particular voltage level through an output terminal is provided. The voltage regulator module may be switched on according to a periodic signal having a periodic signal frequency as a variable. The periodic signal frequency may be tuned to reduce impedance, jitter, or noise.Type: ApplicationFiled: August 17, 2016Publication date: February 22, 2018Inventors: Teik Wah Lim, Ashraf Lotfi