Abstract: Systems, methods, and devices are provided to enable an integrated circuit device of relatively higher capacity. Such an integrated circuit device may include at least two component integrated circuits that communicate with one another. Specifically, the component integrated circuits may communicate through a “stitched silicon interposer” that is larger than a reticle limit of the lithography system used to manufacture the interposer. To achieve this larger size, the stitched silicon interposer may be composed of at least two component interposers, each sized within the reticle limit and each separated from one another by a die seal structure.

Abstract: One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop (PLL) circuit which is programmably coupled to each of the first, second, third and fourth PMA channel circuits. Other embodiments and features are also disclosed.

Abstract: One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop (PLL) circuit which is programmably coupled to each of the first, second, third and fourth PMA channel circuits. Other embodiments and features are also disclosed.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop (PLL) circuit which is programmably coupled to each of the first, second, third and fourth PMA channel circuits. Other embodiments and features are also disclosed.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: A programmable integrated circuit device includes a plurality of specialized processing blocks. Each specialized processing block may be small enough to occupy a single row of logic blocks. The specialized processing blocks may be located adjacent one another in different logic block rows, forming a column of adjacent specialized processing blocks. Each specialized processing block includes one or more multipliers based on carry-save adders whose outputs are combined using compressors. Chain-in and chain-out connections to the compressors allow adjacent specialized processing blocks to be cascaded to form arbitrarily large multipliers. Each specialized processing block also includes a carry-propagate adder, and the carry-propagate added in the final specialized processing block of the chain provides the final result. The size of the multiplication that may be performed is limited only by the number of specialized processing blocks in the programmable integrated circuit device.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.

Abstract: A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.

Abstract: A field programmable gate array (FPGA) has an interface circuit that allows signals to be transmitted directly between the FPGA and a processor. The processor interface (PI) of the FPGA enables the processor to access data at any time from either programmable logic of the FPGA or system registers of the PI. The present invention eliminates the need for external intermediate logic previously required to interface an FPGA and a processor.

Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can be programmed during PLD operations, without reconfiguring the PLD.

Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.

Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.

Abstract: A field programmable gate array (FPGA) which verifies that an incoming bitstream is intended for it prior to writing configuration data to programmable memory cells is described. The bitstream has an identification frame which includes an identification code for the targeted FPGA. A verification circuit in a memory controller verifies whether the bitstream is intended for the FPGA based upon the identification code. If the bitstream is intended for the FPGA, the configuration data is processed and stored in the programmable memory cells. If the bitstream is not intended for the FPGA, the FPGA may enter a standby mode, and the configuration process may be halted until a user resets the FPGA. The verification circuit can help prevent damage that may occur to the FPGA when bitstreams intended for a different size memory cell array are received by the FPGA.

Abstract: Apparatus and method for compressing configuration bitstreams used to program Field Programmable Gate Arrays (FPGAs) and for decreasing the amount of time necessary to configure FPGAs. In a first embodiment of the present invention, a shift register is employed that enables data bits to be shifted multiple positions per clock cycle through the shift register. As a result, the amount of time required to shift the data bits through the shift register can be reduced by 1/N, where N is the number of positions per clock cycle. The shift register also permits the option of shifting bits through the shift register one bit per clock cycle. In a second embodiment of the present invention, control and address bits are employed to more efficiently manage and reduce the size of the configuration bitstream. Accordingly, one embodiment provides the option of loading data into the array of the FPGA by address column in a non-sequential fashion.

Abstract: A programmable function unit (PFU) well adapted for use in a field programmable gate array (FPGA) is disclosed. The PFU utilizes programmable fast ripple logic. A programmable generator and/or a programmable propagator are implemented in look up tables in each PFU block. A multiplexer under control of the propagator determines whether to transmit the carry in from the previous block or to transmit the generator signal.