Abstract: A circuit for sensing gate voltage of a power FET. A switching circuit includes a switching FET having a high voltage rating, its drain coupled to the gate of the power FET, and its source coupled to an output node. A first feedback loop is coupled to the gate of the switching FET to facilitate sensing rising gate voltage. A second feedback loop is coupled to the gate of the switching FET to facilitate sensing falling gate voltage.

Abstract: A circuit for sensing gate voltage of a power FET. A switching circuit includes a switching FET having a high voltage rating, its drain coupled to the gate of the power FET, and its source coupled to an output node. A first feedback loop is coupled to the gate of the switching FET to facilitate sensing rising gate voltage. A second feedback loop is coupled to the gate of the switching FET to facilitate sensing falling gate voltage.

Abstract: A circuit for sensing gate voltage of a power FET. A switching circuit includes a switching FET having a high voltage rating, its drain coupled to the gate of the power FET, and its source coupled to an output node. A first feedback loop is coupled to the gate of the switching FET to facilitate sensing rising gate voltage. A second feedback loop is coupled to the gate of the switching FET to facilitate sensing falling gate voltage.

Abstract: A circuit for sensing gate voltage of a power FET. A switching circuit includes a switching FET having a high voltage rating, its drain coupled to the gate of the power FET, and its source coupled to an output node. A first feedback loop is coupled to the gate of the switching FET to facilitate sensing rising gate voltage. A second feedback loop is coupled to the gate of the switching FET to facilitate sensing falling gate voltage.

Abstract: An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays.

Abstract: An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays.

Abstract: An apparatus includes a delay line having multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal through the delay cells. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the delay line and to output sampled values. The delay line has (i) a finer resolution closer to a target tap and (ii) a coarser resolution farther away from the target tap on each side of the target tap. For example, taps nearer the target tap can be closer to each other in order to support the finer resolution, and taps farther from the target tap can be farther apart from each other in order to support the coarser resolution. The apparatus can further include an encoder configured to encode the sampled values in order to generate an encoded value.

Abstract: A process corner estimation circuit with temperature compensation is included in each die formed from a silicon wafer in order to quickly and easily provide a determination of process corner. The temperature compensation circuitry provides input current to a clock generator, the input current to the clock generator being inversely proportional to the temperature of the die. The clock generator circuit of the indicator circuit includes an array of flip-flop elements and is run at a lower operating voltage, such that the differences in delay in the generated timing signal are accentuated for different process corners. The period of the timing signal is determined using slow and fast clock counters, with the slow clock counting a number of cycles of the timing signal and the fast clock counting a number of cycles of a fixed frequency. The count produced by the fast clock corresponds to the delay in the clock generator circuit, giving a temperature compensated indication of the process corner of the die.

Abstract: A process corner indicator circuit can be included with each die formed from a silicon wafer in order to quickly and easily give a determination of process corner. A clock generator circuit of the indicator circuit can include an array of flip-flop elements, and can be run at a lower operating voltage, such that the differences in delay in the generated timing signal are accentuated for different process corners. The period of the timing signal can be determined using slow and fast clock counters, with the slow clock counting a number of cycles of the timing signal and the fast clock counting a number of cycles of a fixed frequency. The count produced by the fast clock can correspond to the delay in the clock generator circuit, giving an indication of the process corner of the die.

Abstract: The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.

Abstract: A system and method for slack determination in a logic integrated circuit. A launch pulse is input to a circular delay loop circuit. The leading edge of the launch pulse causes a pulse to circulate around the circular delay loop. The number of passes made through the loop by the circulating pulse is counted by a latch/counter circuit. A sample pulse is input to the latch/counter circuit to latch the number of pulse circulations at the leading edge of the sample pulse. The pulse circulation count provides delay information in the circuit that may subsequently be used to adjust a supply voltage in the integrated circuit.

Abstract: The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.

Abstract: A quartz-crystal oscillator circuit substantially reduces the start-up time of the crystal oscillator circuit by utilizing a start-up time reduction circuit that adds additional gain to the crystal oscillator circuit during the start-up period, and removes the additional gain as the oscillator circuit nears steady state operation. Furthermore, the start-up time reduction circuit dynamically monitors the oscillation amplitude. If the build up of oscillation is interrupted, the additional gain will be re-applied.

Abstract: The invention enables the performance of the input and output stages of an I/O circuit to be modified after an IC is manufactured. In one embodiment, the I/O circuit includes an output driver, programmable pre-driver, programmable Schmitt-trigger input buffer, control circuit and logic circuit. Depending on the number of pull-up and pull-down MOS transistor pairs or “cells” that are enabled in the programmable pre-driver and their different sizes, the overall sizing ratio imbalance between the transistors may be programmed. In particular, the high and low trip points for activation of the output driver is related to an imbalance in the overall sizing ratio of transistors enabled in the programmable pre-driver. This affects the timing characteristics of the output driver.

Abstract: The invention is directed to improving power consumption in an integrated circuit by reducing the leakage current of a plurality of MOS transistors with an adaptive back biasing circuit. Since the leakage current characteristic is often non-linear, the optimal back bias voltage (lowest leakage current) is typically identifiable at an inflection point in a graph of the leakage current characteristic versus back bias voltage. Also, depending upon the doping of the MOS transistors (N versus P type) and manufacturing variables for a particular fabrication process, the position of this inflection point can vary between individual integrated circuits that implement substantially the same arrangement of MOS transistors. Despite these issues, the inventive circuit can substantially reduce the leakage current by coupling an adjusted back bias voltage to the substrate of an Integrated Circuit.

Abstract: In a polarity detector circuit for detecting the polarity of monitor sync signals, a clock generator and counter circuit are provided to count clock cycles during the positive and negative portions of the signal. Comparators are used to compare the counter values to predetermined values to determine when one or both of the counters has reached a predefined value. With the proper choice of sampling clock, this digital implementation can be easily optimized for small size and simplicity.

Abstract: A circuit for measuring temperature with all digital components in an integrated circuit. During manufacture, the number of clock period cycles during a known period of time at a predetermined temperature is stored in non-volatile memory. Later, during use of the integrated circuit, a clock circuit is activated and each cycle of its period is counted during a known length of time. Using the previously saved number of clock circuit cycles at a predetermined temperature and a current count of clock cycles for another known length of time, the current period of the clock circuit can be calculated and used to determine the current temperature.

Abstract: In a non-overlap clock generator circuit providing two-phase clock signals, the clock-to-Q delay of memory elements is used to define the non-overlap times. The non-overlap time can be programmed in increments of the clock-to-Q delay of a standard memory element.

Abstract: In a one-shot, the pulse duration is adjustable through the use of a counter and one or more programmable delay lines in one or more of the feedback loops of the one-shot. The one-shot makes use of at least two flip-flops, and the output of the counter resets the flip-flops.

Abstract: In a level shifter for shifting from one voltage to another one, a circuit to eliminate current drain when the low voltage supply is off, includes circuitry for eliminating floating nodes and for providing a distinct output voltage. The circuit includes circuitry for monitoring the low voltage supply and switch in the level shifter when the supply is on. When the supply is off, the input is isolated from the output and an output signal derived from the high voltage supply is provided to the output.