Patents by Inventor Wai Keong Wong
Wai Keong Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9595505Abstract: Embodiments of three dimensional (3D) System-in-Package (SiPs) and methods for producing 3D SiPs having improved heat dissipation capabilities are provided. In one embodiment, the 3D SiP includes a heat-dissipating structure having a first principal surface and a second principal surface opposite the first principal surface. The backside of a first microelectronic device is disposed adjacent and thermally coupled to the first principal surface of the heat-dissipating structure, while the backside of a second microelectronic device is disposed adjacent and thermally coupled to the second principal surface of the heat-dissipating structure. During operation of the 3D SiP, heat generated by the microelectronic devices is conductively transferred to and dissipated through the heat-dissipating structure.Type: GrantFiled: November 25, 2014Date of Patent: March 14, 2017Assignee: NXP USA, INC.Inventors: Shouhui Chen, Guat Kew Teh, Wai Keong Wong
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Publication number: 20160148902Abstract: Embodiments of three dimensional (3D) System-in-Package (SiPs) and methods for producing 3D SiPs having improved heat dissipation capabilities are provided. In one embodiment, the 3D SiP includes a heat-dissipating structure having a first principal surface and a second principal surface opposite the first principal surface. The backside of a first microelectronic device is disposed adjacent and thermally coupled to the first principal surface of the heat-dissipating structure, while the backside of a second microelectronic device is disposed adjacent and thermally coupled to the second principal surface of the heat-dissipating structure. During operation of the 3D SiP, heat generated by the microelectronic devices is conductively transferred to and dissipated through the heat-dissipating structure.Type: ApplicationFiled: November 25, 2014Publication date: May 26, 2016Inventors: SHOUHUI CHEN, GUAT KEW TEH, WAI KEONG WONG
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Patent number: 9293395Abstract: A lead frame for a semiconductor device includes a die paddle and leads situated on a perimeter of the lead frame. The die paddle has a metal frame and a number of substantially linear metal connecting bars within the frame. The connecting bars interconnect different locations of the frame to form a multiple triangles, where a triangular-shaped cavity is formed within each triangle. An overall area of the cavities is greater than an overall area of the connecting bars.Type: GrantFiled: March 19, 2014Date of Patent: March 22, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Wai Keong Wong, Soo Choong Chee, Stanley Job Doraisamy
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Patent number: 9190339Abstract: A method for applying a pressure-sensitive gel material during assembly of an array of pre-singulated packaged semiconductor devices. In the method, pressure-sensitive gel material is dispensed onto a first semiconductor device of the array, where the first semiconductor device is disposed within a first cavity. A first curing process is performed to partially cure the pressure-sensitive gel material in the first cavity. Pressure-sensitive gel material is then dispensed onto another semiconductor device of the array, where the other semiconductor device is disposed within another cavity. The first curing process is initiated before the dispensing of the pressure-sensitive gel material inside of the other cavity is completed and initially cures pressure-sensitive gel material for fewer than all of the pre-singulated packaged semiconductor devices of the array.Type: GrantFiled: February 3, 2014Date of Patent: November 17, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Soon Kang Chan, Voon Kwai Leong, Wai Keong Wong
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Patent number: 9165869Abstract: A lead frame for a semiconductor device has a die flag and leads that surround the die flag. In order to decrease the distance or spacing between inner lead ends and the die flag, which allows for short bond wires for connecting the inner lead ends to a die mounted on the die flag, at least some of the leads are twisted along their lengths to be angled with respect to a die-flag plane. The pitch between such twisted leads can be reduced without resulting in physical contact between adjacent leads, enabling the leads to extend further towards the die flag.Type: GrantFiled: July 11, 2014Date of Patent: October 20, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Soo Choong Chee, Meng Kong Lye, Wai Keong Wong
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Publication number: 20150270195Abstract: A lead frame for a semiconductor device includes a die paddle and leads situated on a perimeter of the lead frame. The die paddle has a metal frame and a number of substantially linear metal connecting bars within the frame. The connecting bars interconnect different locations of the frame to form a multiple triangles, where a triangular-shaped cavity is formed within each triangle. An overall area of the cavities is greater than an overall area of the connecting bars.Type: ApplicationFiled: March 19, 2014Publication date: September 24, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Wai Keong Wong, Soo Choong Chee, Stanley Job Doraisamy
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Publication number: 20150228601Abstract: A semiconductor device is assembled from a rectangular substrate sheet. The substrate sheet has die mounting pads accessible from a first side and package mounting pads accessible from an opposite side. Corner regions of the substrate sheet have receding edges. A semiconductor die is attached to the substrate sheet such that electrodes or bonding pads of the die are mounted to respective die mounting pads of the substrate sheet. An encapsulating material covers the semiconductor die and the first side of the substrate sheet. Corner covering sections of the encapsulating material further cover the receding edges of the corner regions.Type: ApplicationFiled: February 12, 2014Publication date: August 13, 2015Inventors: Wai Keong Wong, Yi Mei Leow, Lan Yit Ong
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Publication number: 20150221572Abstract: A method for applying a pressure-sensitive gel material during assembly of an array of pre-singulated packaged semiconductor devices. In the method, pressure-sensitive gel material is dispensed onto a first semiconductor device of the array, where the first semiconductor device is disposed within a first cavity. A first curing process is performed to partially cure the pressure-sensitive gel material in the first cavity. Pressure-sensitive gel material is then dispensed onto another semiconductor device of the array, where the other semiconductor device is disposed within another cavity. The first curing process is initiated before the dispensing of the pressure-sensitive gel material inside of the other cavity is completed and initially cures pressure-sensitive gel material for fewer than all of the pre-singulated packaged semiconductor devices of the array.Type: ApplicationFiled: February 3, 2014Publication date: August 6, 2015Inventors: Soon Kang Chan, Voon Kwai Leong, Wai Keong Wong
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Patent number: 9099363Abstract: A semiconductor device is assembled from a rectangular substrate sheet. The substrate sheet has die mounting pads accessible from a first side and package mounting pads accessible from an opposite side. Corner regions of the substrate sheet have receding edges. A semiconductor die is attached to the substrate sheet such that electrodes or bonding pads of the die are mounted to respective die mounting pads of the substrate sheet. An encapsulating material covers the semiconductor die and the first side of the substrate sheet. Corner covering sections of the encapsulating material further cover the receding edges of the corner regions.Type: GrantFiled: February 12, 2014Date of Patent: August 4, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Wai Keong Wong, Yi Mei Leow, Lan Yit Ong
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Patent number: 9006874Abstract: A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.Type: GrantFiled: January 6, 2014Date of Patent: April 14, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Wai Keong Wong, Kok Leong Chan, Wei Kee Chan
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Publication number: 20140120664Abstract: A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.Type: ApplicationFiled: January 6, 2014Publication date: May 1, 2014Inventors: Wai Keong Wong, Kok Leong Chan, Wei Kee Chan
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Patent number: 8643159Abstract: A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.Type: GrantFiled: April 9, 2012Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Wai Keong Wong, Kok Leong Chan, Wei Kee Chan
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Publication number: 20130264693Abstract: A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.Type: ApplicationFiled: April 9, 2012Publication date: October 10, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Wai Keong WONG, Kok Leong CHAN, Wei Kee CHAN
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Patent number: 8519519Abstract: A semiconductor device includes a lead frame that has a die interconnect portion and at least first and second die pads. The die interconnect portion is isolated from the die pads. The device also includes a first die and a second die attached to the first and second die pads and electrically connected to each other by way of the die interconnect portion. The first die is encapsulated in a first medium and the second die is encapsulated in a second medium, the first medium being different from the second medium.Type: GrantFiled: November 3, 2010Date of Patent: August 27, 2013Assignee: Freescale Semiconductor Inc.Inventors: Beng Siong Lee, Guat Kew Teh, Wai Keong Wong
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Publication number: 20120318853Abstract: A heater block for a wire bonding system includes a mounting base configured to receive a lead frame and a semiconductor die mounted on the lead frame. A heating structure is removably coupled to a top surface of the mounting base. The heating structure includes a central heating surface and side heating panels surrounding the central heating surface. The heating structure selectively heats wire bonding areas of the lead frame.Type: ApplicationFiled: June 15, 2011Publication date: December 20, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Wai Keong Wong, Jimmy Low, Raymund Francis Xavier
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Patent number: 8198143Abstract: A mold (10) including a first mold part (12) and a second mold part (14) define a mold cavity (16) therebetween. A gate (18) is formed in at least one of the first and second mold parts (12) and (14) such that the gate (18) communicates with the mold cavity (16). A vent (20) having a constricted portion (22) is arranged to communicate with the mold cavity (16). A substrate (28) including a base substrate (30) and an electrically conductive pattern (32) and (34) formed on the base substrate (30) may be received in the mold (10). A solder resist layer (36) is formed on the base substrate (30) and a portion of the electrically conductive pattern (32). A plurality of grooves (38) and (40) is formed in a staggered arrangement around a periphery of a molding area (42) on the substrate (28).Type: GrantFiled: April 29, 2011Date of Patent: June 12, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Poh Leng Eu, Boon Yew Low, Wai Keong Wong
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Publication number: 20120104583Abstract: A semiconductor device includes a lead frame that has a die interconnect portion and at least first and second die pads. The die interconnect portion is isolated from the die pads. The device also includes a first die and a second die attached to the first and second die pads and electrically connected to each other by way of the die interconnect portion. The first die is encapsulated in a first medium and the second die is encapsulated in a second medium, the first medium being different from the second medium.Type: ApplicationFiled: November 3, 2010Publication date: May 3, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Beng Siong Lee, Guat Kew Teh, Wai Keong Wong
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Publication number: 20110244637Abstract: A mold (10) including a first mold part (12) and a second mold part (14) define a mold cavity (16) therebetween. A gate (18) is formed in at least one of the first and second mold parts (12) and (14) such that the gate (18) communicates with the mold cavity (16). A vent (20) having a constricted portion (22) is arranged to communicate with the mold cavity (16). A substrate (28) including a base substrate (30) and an electrically conductive pattern (32) and (34) formed on the base substrate (30) may be received in the mold (10). A solder resist layer (36) is formed on the base substrate (30) and a portion of the electrically conductive pattern (32). A plurality of grooves (38) and (40) is formed in a staggered arrangement around a periphery of a molding area (42) on the substrate (28).Type: ApplicationFiled: April 29, 2011Publication date: October 6, 2011Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Poh Leng EU, Boon Yew Low, Wai Keong Wong
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Patent number: 8016183Abstract: A method and an adjustable clamp system for clamping a die assembly during wire bonding. The system includes at least one pair of opposing base walls, each of the base walls has a base clamping surface. There is at least one pair of clamping members, each one of the clamping members being movable towards a respective base clamping surface to thereby clamp a lead frame of the die assembly. A die assembly support is disposed between the pair of opposing base walls and the die assembly support and pair of opposing base walls provide a cavity. There is a position sensor coupled to a controller and there is also a drive that is controllable by the controller. The drive provides movement of the die assembly support relative to each the base clamping surface to thereby adjust a depth of the cavity.Type: GrantFiled: November 5, 2009Date of Patent: September 13, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Wai Keong Wong, Sik Pong Lee
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Patent number: 7956471Abstract: A mold (10) including a first mold part (12) and a second mold part (14) define a mold cavity (16) therebetween. A gate (18) is formed in at least one of the first and second mold parts (12) and (14) such that the gate (18) communicates with the mold cavity (16). A vent (20) having a constricted portion (22) is arranged to communicate with the mold cavity (16). A substrate (28) including a base substrate (30) and an electrically conductive pattern (32) and (34) formed on the base substrate (30) may be received in the mold (10). A solder resist layer (36) is formed on the base substrate (30) and a portion of the electrically conductive pattern (32). A plurality of grooves (38) and (40) is formed in a staggered arrangement around a periphery of a molding area (42) on the substrate (28).Type: GrantFiled: November 12, 2008Date of Patent: June 7, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Poh Leng Eu, Boon Yew Low, Wai Keong Wong