Abstract: A first apparatus includes at least one scan chain. Each of the at least one scan chain includes scan cells coupled together. Each scan cell in the at least one scan chain includes a first type of scan cell when a reset state of the scan cell is a first state, and a second type of scan cell when the reset state of the scan cell is a second state. One or more scan chains of the at least one scan chain includes at least one of the first type of scan cell and at least one of the second type of scan cell. A second apparatus includes first and second sets of scan chains including flip-flops without both set and reset functionality. Each of the flip-flops in the first and second sets of scan chains has a reset state of a first state and a second state, respectively.

Abstract: Circuits and methods for reducing leakage are provided. In one example, a system includes circuitry to reset a particular logic circuit to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit includes the combinational logic as well as flip flops that output a state to the combinational logic. Some of the flip flops are “SET” flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are “RESET” flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

Abstract: Circuits and methods for reducing leakage are provided. In one example, a system includes circuitry to reset a particular logic circuit to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit includes the combinational logic as well as flip flops that output a state to the combinational logic. Some of the flip flops are “SET” flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are “RESET” flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

Abstract: Systems and methods for efficiently generating electromigration reliability data for physical cells in an integrated circuit cell library are disclosed. Data for tables of electromigration susceptibility can be iteratively generated for multiple capacitive loadings on a cell output and for multiple transition times of a cell input. Each iteration can include simulating electrical performance of the physical cell and identifying a region with the largest ratio of current density to electromigration reliability limit. Between iterations, the data period of the input signal is updated using the ratio of current density to electromigration reliability limit and a relationship between currents and data period. Iterations may end when the ratio is close to one. The result can be used to evaluate electromigration reliability of an integrated circuit design and modify the design accordingly.

Abstract: A first apparatus includes at least one scan chain. Each of the at least one scan chain includes scan cells coupled together. Each scan cell in the at least one scan chain includes a first type of scan cell when a reset state of the scan cell is a first state, and a second type of scan cell when the reset state of the scan cell is a second state. One or more scan chains of the at least one scan chain includes at least one of the first type of scan cell and at least one of the second type of scan cell. A second apparatus includes first and second sets of scan chains including flip-flops without both set and reset functionality. Each of the flip-flops in the first and second sets of scan chains has a reset state of a first state and a second state, respectively.