Abstract: A phase shifter is implemented using a polyphase filter. The filter is preferably a linear phase Finite Impulse Response (FIR) filter. The amount of delay imparted by the phase shifter is determined by a particular set of coefficients selected from a plurality of such coefficients. Storage requirements are reduced by taking advantage of symmetries in the coefficients for the filters. Memory requirements are further reduced by partitioning the polyphase filter into two polyphase filters and using one to set a rough delay amount and the other to set a fine delay amount between rough delay amount settings. The particular amount of delay may be set by an external synchronization signal.

Abstract: A decimation filter implements selective decimation ratios by arranging a plurality of sinc filters in different pipeline arrangements to produce the desired ratio. Power savings area achieved by implementing the sinc filters as FIR sinc filters and by implementing multiplications using look up tables. One approach uses a fixed first stage filter and one or more second stage sinc filters selected from the group comprising two 4th order, 5 tap sinc filters, a 4th order, 9 tap sinc filter; a 5th order, 6 tap sinc filter and a 6th order 7 tap sinc filter. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

Abstract: Power available to a delta sigma modulator is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected to reduce power corruption and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.

Abstract: A switched converter uses two series connected complementary CMOS devices and has a square wave source for activating one CMOS device while deactivating the other; and a break before make circuit connected between the square wave source and said complementary CMOS devices to ensure that one device is substantially completely off before the other device turns on. The switched converter is programmable as to frequency, phase and duty cycle.

Abstract: A multistage comparator is calibrated to remove quasi-autozero voltages derived from the native comparator offset and autozero switch charge injection offsets. A multistage comparator includes a plurality of series connected amplifiers each having a programmable source, and further including a latch. A calibration method for a multistage comparator includes calibrating the first of a series of amplifiers first for both voltage offset and charge injection errors thereby to remove the quasi-autozero voltage and charge injection offsets.

Abstract: A front end for capturing seismic signals uses a voltage doubling circuit and an analog to digital converter (ADC) having different power levels available during respective operational phases. Power available the ADC is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. Increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected for the ADC to reduce power consumption for a delta sigma modulator used in the ADC and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.

Abstract: A multiply add carry (MAC) circuit correctly determines the value of a carry bit when an operation X*Y+Z is undertaken, where X, Y and Z are real numbers and where an accumulator and rounding are utilized. The circuit (1) determines if the product X*Y is negative, (2) determines if the value in the accumulator is negative, (3) determines if a round bit propagates all the way to the most significant bit (MSB) position, (4) determines if the result X*Y+Accumulator+round is negative; and (5) determines a correct carry bit based on the other determinations.

Abstract: A high performance test signal generator uses a digital to analog converter which converts an N-bit digital signal, such as provided by a computer waveform generator or by a CDROM into an M-bit upsampled digital signal. The M-bit digital signal is applied to an M-bit digital to analog converter to produce an analog output signal. The analog output signal is sampled and fed back across, the discrete time/continuous time interface to the input of the conversion circuit. The test signal generator has very low power consumption yet meets very strict noise and linearity requirements. The test signal generator can be used for testing seismic sensors such as geophones or hydrophones.

Abstract: A multi-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.

Abstract: A integrated circuit digital to analog converter converts an M-bit digital signal to an analog output signal. The analog output signal can be used to drive external devices such as an off-chip driver. The output of the external device is sampled and fed back across the discrete time/continuous time interface on the chip to the input of the analog to digital converter. Taking the feedback point after the external device ensures relatively high performance for noise and linearity using relatively low performance components, both on and off the chip.

Abstract: A digital to analog converter converts an N-bit digital signal into an M-bit digital signal and provides the M-bit digital signal to a conversion circuit which converts the M-bit signal to an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. An interpolation filter is used to increase the apparent sampling rate of the incoming N-bit signal.

Abstract: A digital to analog converter utilizes two discrete time processing stages, such as switched capacitor integrator circuits, operating at different sampling rates when converting the digital input signal to an analog signal. Use of two different sampling rates relaxes the requirements on antialias filters used in the continuous time processing.

Abstract: A 1-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.